w83977eg Winbond Electronics Corp America, w83977eg Datasheet - Page 52

• Manufacturer Part Number: w83977eg
• Description: Winbond Isa I/o W83977ef W83977eg
• Manufacturer: Winbond Electronics Corp America

Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
6.2.6
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
Bit
3
0
0
0
1
0
0
other bits of UFR are programmed.
out interrupt is pending.
this bit will be set to a logical 0.
Bit
2
0
1
1
1
0
0
ISR
Interrupt Status Register (ISR) (Read only)
Bit
1
0
1
0
0
1
0
Bit
0
1
0
0
0
0
0
Interrupt
priority
First
Second
Second
Third
Fourth
7
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TABLE 6-4 INTERRUPT CONTROL FUNCTION
6
Interrupt Type
UART Receive
Status
RBR Data Ready
FIFO Data Timeout
TBR Empty
Handshake status
0
5
4
0
-
3
INTERRUPT SET AND FUNCTION
W83977EF-AW/W83977EG-AW
2
-50-
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
reached
1
0
2. PBER =1
4. TDCD = 1
2. TDSR = 1
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority is
Read HSR
third)
-