w83977eg Winbond Electronics Corp America, w83977eg Datasheet - Page 47

• Manufacturer Part Number: w83977eg
• Description: Winbond Isa I/o W83977ef W83977eg
• Manufacturer: Winbond Electronics Corp America

*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
BDLAB =
BDLAB =
BDLAB =
BDLAB =
BDLAB =
REGISTER ADDRESS
+ 0
+ 0
+ 1
+ 2
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
+ 1
0
0
0
1
1
BASE
UART Status
User Defined
Divisor Latch
Divisor Latch
(Read Only)
(Write Only)
(Read Only)
(Write Only)
UART FIFO
Transmitter
Handshake
Handshake
Baudrate
Receiver
Register
Register
Interrupt
Register
Interrupt
Register
Register
Register
Register
Register
Register
Register
Baudrate
Control
Control
Control
Control
Status
Status
Buffer
Buffer
UART
High
Low
RBR
UCR
HCR
USR
HSR
UDR
TBR
UFR
BHL
ICR
BLL
ISR
RBR Data
RBR Data
RX Data
TX Data
Terminal
Toggling
Interrupt
(ERDRI)
Interrupt
Pending
(TCTS)
Enable
Enable
(DLS0)
Length
Ready
Ready
Ready
Select
(DTR)
(RDR)
FIFO
"0" if
Data
Data
Bit 0
Bit 0
Bit 0
CTS
Bit 0
Bit 0
Bit 8
0
TABLE 6-1 UART Register Bit Map
(ETBREI)
RX Data
Toggling
Interrupt
Interrupt
Request
TX Data
Overrun
(TDSR)
(DLS1)
Enable
Length
Empty
Status
RCVR
Select
(OER)
Bit (0)
Reset
(RTS)
Send
FIFO
Error
Data
DSR
Bit 1
Bit 1
TBR
Bit 1
Bit 1
Bit 1
Bit 9
to
1
W83977EF-AW/W83977EG-AW
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
(EUSRI)
Interrupt
TX Data
Interrupt
Multiple
(MSBE)
(PBER)
Enable
Enable
(FERI)
Status
Bit (1)
Reset
Bit 10
XMIT
FIFO
Input
Error
Edge
Bit 2
Bit 2
Bit 2
Bit 2
USR
RI
BIT NUMBER
2
-45-
RX Data
Toggling
TX Data
Interrupt
(EHSRI)
Interrupt
No Stop
Bit (2)**
(NSER)
(TDCD)
Enable
Enable
Enable
Status
Select
(PBE)
Parity
Bit 11
Mode
HSR
DMA
Error
DCD
Bit 3
Bit 3
Bit 3
Bit 3
IRQ
Bit
Bit
3
Loopback
Reserved Reversed
Detected
RX Data
TX Data
Internal
to Send
Enable
Enable
(EPE)
(SBD)
(CTS)
Parity
Bit 12
Silent
Clear
Even
Bit 4
Bit 4
Byte
Bit 4
Bit 4
Publication Release Date: Apr. 2006
4
0
0
RX Data
TX Data
Bit Fixed
Data Set
(TBRE)
Enable
PBFE)
Empty
Ready
(DSR)
Parity
Bit 13
Bit 5
Bit 5
TBR
Bit 5
Bit 5
5
0
0
0
RX Data
Indicator
TX Data
Enabled
Interrupt
Silence
(TSRE)
Enable
Empty
FIFOs
Active
(LSB)
(SSE)
Bit 14
Level
Ring
Bit 6
Bit 6
TSR
Bit 6
Bit 6
(RI)
Set
RX
**
6
0
0
Revision 1.2
Access Bit
Indication
RX Data
Baudrate
(BDLAB)
RX FIFO
(RFEI) **
Enabled
Interrupt
TX Data
Divisor
Carrier
Detect
FIFOs
Active
(MSB)
(DCD)
Latch
Bit 15
Level
Error
Data
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0