pdi1394l41 NXP Semiconductors, pdi1394l41 Datasheet - Page 7

• Manufacturer Part Number: pdi1394l41
• Description: 1394 Content Protection Av Link Layer Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.0 APPLICATION DIAGRAM
9.0 PIN DESCRIPTION
9.1 Host Interface
2000 Dec 01
13, 14, 15, 16, 19,
26, 27, 28, 29, 30,
1, 2, 3, 4, 7, 8, 9,
1394 content protection AV link layer controller
20, 21, 22
31, 32, 33
PIN No.
10
25
37
38
39
40
41
42
45
46
36
HOST CONTROLLER
MPEG OR DVC
MPEG OR DVC
PIN SYMBOL
DECODER
DECODER
HIF AD[7:0]
HIF D[15:8]
HIF 16BIT
HIF A[7:0]
HIF WRN
HIF WAIT
HIF INTN
HIF RDN
RESETN
HIF MUX
HIF CSN
HIF ALE
HIF A8
INTERRUPT & CONTROL
I/O
I/O
I/O
I/O
O
O
INTERFACE
INTERFACE
I
I
I
I
I
I
I
I
ADDRESS 9/
DATA 16/
AV
AV
NAME AND FUNCTION
Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.
Host Interface Data 15 (MSB) through 8. Only used in 16 bit access mode (HIF
16BIT = HIGH).
Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal
registers. See description of Host Interface for addressing rules (Section 12.5).
Control bit used to indicate the first byte/word of a read function or the last byte/word of a write
function so that the data quadlet is fetched or stored. See Section 12.5 for more information
regarding the host interface.
Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control
and status registers.
Write enable. When asserted (LOW) in conjunction with HIF CSN, a write to the PDI1394L41
internal registers is requested. (NOTE: HIF WRN and HIF RDN : if these are both LOW in
conjunction with HIF CSN, then a write cycle takes place. This can be used to connect CPUs
that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the
R/W_N line to the HIF WRN and tie HIF RDN LOW.)
Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L41. Read the General
Interrupt Register for more information. This pin is open drain and requires a 1K pull-up
resistor.
Address latch enable. Used in multiplex mode only.
Read enable. When asserted (LOW) in conjunction with HIF CSN, a read of the PDI1394L41
internal registers is requested.
Wait signal. Signals Host interface in WAIT condition when HI. See Section 12.5.
Reset (active LOW). The asynchronous master reset to the PDI1394L41.
Host interface mode pin. When LOW HIF operates in 8 bit mode. When HIGH HIF operates in
16 bit mode.
Host interface mode pin. When LOW HIF operates in non-multiplex mode, when HIGH HIF
operates in multiplex mode. When HIGH, the low-order eight address bits are multiplexed with
data on HIF AD[7:0], otherwise they are non-multiplexed and supplied on A[7:0].
PDI1394L41
AV LINK
4
INTERFACE
PHY–LINK
PDI1394Pxx
PHY
1394 CABLE
INTERFACE
PDI1394L41
Preliminary specification
SV01023