gtl2010 NXP Semiconductors, gtl2010 Datasheet - Page 2

• Manufacturer Part Number: gtl2010
• Description: 10-bit Gtl Processor Voltage Clamp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURES
APPLICATIONS
ORDERING INFORMATION
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
24-Pin Plastic TSSOP
24-Pin Plastic HVQFN
2004 Jul 28
10-bit bi-directional low voltage translator
Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL,
GTL+, LVTTL/TTL and 5 V CMOS levels
Provides bi-directional voltage translation with no direction pin
Low 6.5
(Sn/Dn)
Supports hot insertion
No power supply required - Will not latch up
5 V tolerant inputs
Low stand-by current
Flow-through pinout for ease of printed circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V per JESD22-C101
Packages offered: TSSOP24, HVQFN24
Any application that requires bi-directional or unidirectional
voltage level translation from any voltage from 1.0 V to 5.0 V to
any voltage from 1.0 V to 5.0 V
The open drain construction with no direction pin is ideal for
bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V)
processor I
I
signal levels.
10-bit bi-directional low voltage translator
2
C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL
PACKAGES
RDS
2
C port translation to the normal 3.3 V and/or 5.0 V
ON
resistance between input and output pins
TEMPERATURE RANGE
–40 C to +85 C
–40 C to +85 C
ORDER CODE
GTL2010PW
GTL2010BS
2
DESCRIPTION
The Gunning Transceiver Logic — Transceiver Voltage Clamps
(GTL–TVC) provide high-speed voltage translation with low
ON-state resistance and minimal propagation delay. The GTL2010
provides 10 NMOS pass transistors (Sn and Dn) with a common
gate (G
allows bi-directional voltage translations between 1.0 V and 5.0 V
without use of a direction pin.
When the Sn or Dn port is LOW the clamp is in the ON-state and a
low resistance connection exists between the Sn and Dn ports.
Assuming the higher voltage is on the Dn port, when the Dn port is
HIGH, the voltage on the Sn port is limited to the voltage set by the
reference transistor (S
is pulled to V
seamless translation between higher and lower voltages selected by
the user, without the need for directional control.
All transistors have the same electrical characteristics and there is
minimal deviation from one output to another in voltage or
propagation delay. This is a benefit over discrete transistor voltage
translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical,
S
Sn/Dn transistors, allowing for easier board layout. The translator’s
transistors provides excellent ESD protection to lower voltage
devices and at the same time protect less ESD resistant devices.
REF
and D
REF
) and a reference transistor (S
REF
CC
by the pull-up resistors. This functionality allows a
can be located on any of the other ten matched
TOPSIDE MARK
GTL2010
REF
2010
). When the Sn port is HIGH, the Dn port
REF
DWG NUMBER
and D
SOT355–1
SOT616–1
Product data sheet
GTL2010
REF
). The device