pxb4340e Infineon Technologies Corporation, pxb4340e Datasheet - Page 71

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pxb4340e

Manufacturer Part Number
pxb4340e
Description
Atm Oam Processor Aop
Manufacturer
Infineon Technologies Corporation
Datasheet

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These registers define the thresholds in the PM data collection algorithm described in
The referenced counters are located in the PM Data Collection RAM (see
Read/write Address A0
Value after reset 0000
Recommended value 0003
UMLOST(15:0) holds the global MLOST threshold (CLP0+1 cells) for the PM data collection in
upstream direction. A PM block with more than MLOST lost cells is considered severely errored
by the data collection algorithm. Accordingly the SECB counter is incremented. If less or equal
MLOST cells are missing the lost cell counters are incremented.
Read/write Address A1
Value after reset 0000
Recommended value 0002
UMISINS(15:0) holds the global MMISINS threshold for the PM data collection in upstream
direction. A PM block with more than MMISINS misinserted cells is considered severely errored
by the data collection algorithm. Accordingly the SECB counter is incremented. If less or equal
MMISINS cells are misinserted the misinserted cell counters are incremented.
Read/write Address A2
Value after reset 0000
Recommended value 0003
UMLOST0(15:0) holds the global MLOST0 threshold (CLP0 cells only) for the PM data collection
in upstream direction. A PM block with more than MLOST0 lost cells is considered severely
errored by the data collection algorithm. Accordingly the SECB counter is incremented. If less
or equal MLOST0 cells are missing the lost cell counters are incremented.
Read/write Address A3
Value after reset 0000
Recommended value 0003
UMERR(15:0) holds the global MERR threshold for the PM data collection in upstream direction.
A BR cell carrying a block error result BLER value greater than MERR denotes a severely
errored block. Accordingly the SECB counter is incremented. If BLER is less or equal MERR the
BLER value is added to the error counter ERRC.
Data Sheet
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3.9.6).
04.2000
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