ncn6024 ON Semiconductor, ncn6024 Datasheet - Page 9

• Manufacturer Part Number: ncn6024
• Description: Compact And Low Cost Smart Card Interface Ic
• Manufacturer: ON Semiconductor

NOTE:
POWER SUPPLY
supplies: VDD and VDDP.
interface. The applied VDD range can go from 2.7 V up to
5.5 V. If VDD goes below 2.35 V typical (UVLO
power-down sequence is automatically performed. In that
case the interrupt (INT) pin is set Low.
followed by a Low Drop−Out (LDO) regulator is used to
provide the 3 V or 5 V power supply voltage (CRD_VCC)
to the card. VDDP is the converter’s input voltage for which
2 voltage ranges can be considered: 3.0 V v VDDP v 5.5 V
with ICC v 15 mA and 4.5 V v VDDP v 5.5 V with ICC
v 65 mA. VUP is the charge−pump converter’s output. It is
connected to the LDO input. A reservoir capacitor of 100 nF
is connected to VUP. CRD_VCC is the LDO output. Even
if the converter can operate with a single output reservoir
capacitor as low as 100 nF at CRD_VCC, it is recommended
to use a capacitor of at least 320 nF in order to satisfy
optimally the datasheet specifications (100 nF + 220 nF or
330 nF or 100 nF + 330 nF or 470 nF). To minimize dI/dt
effects, the fly capacitor (100 nF) and the reservoir
capacitors VUP and CRD_VCC have to be connected as
close as possible to the corresponding device’s pin and
feature very low ESR values (lower than 50 mW). The fly
capacitor is connected between C1 and C2. The decoupling
capacitors on VDD and VDDP respectively 100 nF and
10 mF have also to be connected close to the respective IC
pins.
over the VDDP range (5 V ± 10%), the absolute maximum
current being internally limited below 150 mA (Typical at
SMART CARD INTERFACE SECTION, CRD_IO, CRD_AUX1, CRD_AUX2, CRD_CLK, CRD_RST, CRD_PRES,
CRD_PRES
11, 12,
13, 16
9, 10
9, 10
The NCN6024 smart card interface has two power
VDD is usually common to the system controller and the
A built−in charge−pump−based DC/DC converter
The CRD_VCC pin can source up to 65 mA continuously
Pin
15
16
Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
T
I
I
Temp
Symbol
CRD_CLK
CRD_RST
I
debounce
CRD_IO
t
deact
|I
|I
t
act
(V
IH
IL
|
|
DD
SD
= 3.3 V; V
CRD_PRES, CRD_PRES
Low level input leakage current, V
CRD_PRES
CRD_PRES
High level input leakage current, V
CRD_PRES
CRD_PRES
Debounce Time CRD_PRES and CRD_PRES (Note 5)
CRD_IO, CRD_AUX1, CRD_AUX2 Current Limitation
CRD_CLK Current Limitation
CRD_RST Current Limitation
Activation Time (Note 5)
Deactivation Time (Note 5)
Shutdown Temperature
DDP
= 5 V; T
amb
= 25°C; F
Rating
IH
CLKIN
IL
VDD
http://onsemi.com
= V
= 0 V
DD
= 10 MHz)
) a
9
110 mA). CRD_VCC can stay in the range 4.6 V – 5.30 V
during current transient up to 200 mA (peak current) over
less than 400 ns of current pulse duration such as the charge
transient is lower than 40 nAs.
They can be applied to the interface in any sequence. After
powering the device INT remains Low until a card is
inserted.
SUPPLY VOLTAGE MONITORING
On Reset (POR) circuitry and the under voltage lockout
(UVLO) detection (VDD voltage dropout detection).
PORADJ pin allows the user, according to the considered
application, to adjust the VDD UVLO threshold. If not used
PORADJ pin is connected to Ground.
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no
further signal can be provided or supported during this
period. Such initialization takes place when the input
voltage rises between 2 V to 2.6 V about typical.
reached the minimum 2.7 V. Considering this, the NCN6024
will detect an Under-Voltage situation when the input supply
voltage will drop below 2.35 V typical. When VDD goes
down below the UVLO falling threshold a deactivation
sequence is performed.
the VDD supply (8 ms reset pulse).
according to the below relationship considering an external
There’s no specific sequence for applying VDD or VDDP.
The supply voltage monitoring block includes the Power
The input supply voltage is continuously monitored to
The system is ready to operate when the input voltage has
The device is inactive during power-on and power-off of
PORADJ pin is used to modify the UVLO threshold
Min
30
30
5
−
−
−
−
Typ
150
5
5
8
−
−
−
−
−
Max
220
100
10
10
15
70
20
11
1
1
−
Unit
mA
mA
mA
ms
mA
°C
ms
ms