pi2eqx5864d Pericom Semiconductor Corporation, pi2eqx5864d Datasheet - Page 9

• Manufacturer Part Number: pi2eqx5864d
• Description: 5.0gbps 4-lane Pcie? 2.0 Redrivertm With Equalization, Emphasis, & I2c Control
• Manufacturer: Pericom Semiconductor Corporation

Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowl-
edge clock pulse, the PI2EQX5864D will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW
during the HIGH period of this clock pulse as indicated in the I
acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5864D will watch the next
byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the
following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop
bit. For a write cycle, the first data byte following the address byte is a dummy or fill byte that is not used by the PI2EQX5864D.
This byte is provided to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most
significant bit (MSB) first. After each block write, address pointer will reset to byte 0.
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold
Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electri-
cal idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then
SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
BYTE 1 - Receiver Detect Output Register (RX50)
RX50_xy = 1 = load detected, RX50_xy = 0 = No receiver found
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is at a
logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50 regis-
ter is read-only, and is undefined after power-up until a Receiver Detection cycle completes.
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Bit
Type
Power-on
State
Bit
Type
Power-on
State
Name
Name
7
R
X
RX50_A0
7
R
X
SIG_A0
6
RX50_B0
R
X
6
R
X
SIG_B0
5
RX50_A1
R
X
5
R
X
SIG_A1
10-0172
4
R
X
RX50_B1
4
SIG_B1
R
X
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
2
C Data Transfer diagram. The PI2EQX5864D will generate an
9
3
R
X
RX50_A2
3
R
X
SIG_A2
2
R
X
RX50_B2
2
R
X
SIG_B2
www.pericom.com
1
R
X
1
R
X
RX50_A3
SIG_A3
PI2EQX5864D
PS 0.1
0
R
X
0
SIG_B3
R
X
RX50_B3
06/04/10