pi2eqx5864d Pericom Semiconductor Corporation, pi2eqx5864d Datasheet - Page 18

• Manufacturer Part Number: pi2eqx5864d
• Description: 5.0gbps 4-lane Pcie? 2.0 Redrivertm With Equalization, Emphasis, & I2c Control
• Manufacturer: Pericom Semiconductor Corporation

SDA and SCL I/O for I
Characteristics of the SDA and SCL bus lines for F/S-mode I
Notes:
1. All values referred to VIHmin and VILmax levels.
2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region
of the falling edge of SCL.
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Symbol
V IH
V IL
V OL
V hys
f SCL
t HD;STA
t LOW
t HIGH
t SU;STA
t HD;DAT
t SU;DAT
t r
t f
t SU;STO
t BUF
C b
Symbol
SCL clock frequency
Hold time (repeated) START condition. After
this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Buss free time between a STOP and STOP
condition
Capacitive load for each bus line
Parameter
Parameters
DC input logic high
DC input logic low
DC output logic low
Hysteresis of Schmitt trigger input
2
C-bus (V
DD
= 1.2 ± 0.05v, T
10-0172
A
= 0 to 70°C)
Conditions
Conditions
I OL = 3mA
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization
18
2
C-bus devices
Min.
1.1
-0.3
0.2
0
4.0
4.7
4.0
4.7
5.0
250
–
4.0
4.7
–
Min.
(1)
Typ.
Typ.
www.pericom.com
Max.
3.6
0.7
0.4
100
–
–
–
–
–
–
1000
300
–
–
400
Max.
PI2EQX5864D
PS 0.1
Units
V
kHz
µs
ns
µs
pF
Unit
06/04/10