pi2eqx5864 Pericom Semiconductor Corporation, pi2eqx5864 Datasheet - Page 7

• Manufacturer Part Number: pi2eqx5864
• Description: 5.0gbps 4-lane Pcie Gen2 Redriver With I2c Control
• Manufacturer: Pericom Semiconductor Corporation

Confi guration Register Summary
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold
Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electri-
cal idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then
SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
Byte 1 - Receiver Detect Output Register (RX50)
RX50_xy = 1 = load detected, RX50_xy = 0 = No reciever found
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is
at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50
register is read-only, and is undefi ned after power-up until a Receiver Detection cycle completes.
Byte
0
1
2
3
4
5
6
7
8
9
10
11
Power-on
Power-on
Name
Name
Type
State
Type
State
Bit
Bit
07-0277
Mnemonic
SIG
RX50
LBEC
INDIS
OUTDIS
RESET
PWR
RXDE
AEOC
BEOC
RSVD
RSVD
RX50_A0
SIG_A0
R
X
7
X
R
7
Function
Signal Detect, indicates valid input signal level
Receiver Detect Output, indicates whether a receiver load was detected
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (pre-
emphasis or de-emphasis)
Channel Input Disable, controls whether s channels input buffer is enabled or disabled
Channel Output Disable: Controls whether a channels output buffer is enabled or disabled
Channel Reset
Power Down Control, enables power down for each channel individually
Receiver Detect Enable, controls the receiver detect operation
A-Channels Equalizer and Output Control
B-Channels Equalizer and Output Control
Reserved
Reserved
RX50_B0
SIG_B0
X
X
R
R
6
6
RX50_A1
SIG_A1
X
X
R
R
5
5
RX50_B1
SIG_B1
X
R
X
R
4
4
7
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I
RX50_A2
SIG_A2
X
R
X
R
3
3
RX50_B2
SIG_B2
X
R
X
R
2
2
RX50_A3
SIG_A3
R
X
R
X
1
1
PS8934A
PI2EQX5864
2
C Control
RX50_B3
SIG_B3
X
R
0
R
X
0
01/21/08