lm2512asnx National Semiconductor Corporation, lm2512asnx Datasheet - Page 17

• Manufacturer Part Number: lm2512asnx
• Description: Mobile Pixel Link Mpl-1 , 24-bit Rgb Display Interface Serializer With Optional Dithering And Look Up Table
• Manufacturer: National Semiconductor Corporation

Application Information
SYSTEM BANDWIDTH CALCULATIONS
For a HVGA (320 X 480) application with the following as-
sumptions: 60 Hz +/−5% refresh rate, 10% blanking,
RGB666, and 2 MD Lanes and following calculations can be
made:
Calculate PCLK - 320 X 480 X 1.1 X 60 X 1.05 = 10.6 MHz
PCLK
Calculate MC rate - since the application is 2 MD lanes, PCLK
X 6 is the MC rate or 63.87 MHz. Also check that this MC rate
does not exceed the MC maximum rate for the chipset.
Calculate MD rate - MPL uses both edges of the MC to send
serialized data, thus data rate is 2X the MC rate, or 127.7
Mbps per MD lane in our example.
Calculate the application throughput - using 2 MD lanes,
throughput is 2 X of the MD rate or 255.5 Mbps of raw band
width.
For a VGA (640 X 480) application with the following assump-
tions: 55 Hz +/−5% refresh rate, 10% blanking, RGB666, and
3 MD Lanes and following calculations can be made:
Calculate PCLK - 640 X 480 X 1.1 X 55 X 1.05 = 19.5 MHz
PCLK
Calculate MC rate - since the application is 3 MD lanes, PCLK
X 4 is the MC rate or 78.1 MHz. Also check that this MC rate
does not exceed the MC maximum rate for the chipset.
Calculate MD rate - MPL uses both edges of the MC to send
serialized data, thus data rate is 2X the MC rate, or 156 Mbps
per MD lane in our example.
Calculate the application throughput - using 3MD lanes,
throughput is 3X of the MD rate or 468 Mbps of raw band
width.
SYSTEM CONSIDERATIONS
When employing the MPL SER/DES chipset in place of a
parallel video bus, a few system considerations must be taken
into account. Before sending video data to the display, the
SER/DES must be ready to transmit data across the link. The
MPL link must be powered up, and the PLL must be locked
and the DES calibrated.
FLEX CIRCUIT RECOMMENDATIONS
The MPL lines should generally run together to minimize any
trace length differences (skew). For impedance control and
also noise isolation (crosstalk), guard ground traces are rec-
ommended in between the signals. Commonly a Ground-
Signal-Ground (GSGSGSG) layout is used. Locate fast edge
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rate and large swing signals further away to also minimize any
coupling (unwanted crosstalk). In a stacked flex interconnect,
crosstalk also needs to be taken into account in the above
and below layers (vertical direction). To minimize any cou-
pling locate MPL traces next to a ground layer. Power rails
also tend to generate less noise than LVCMOS so they are
also good candidates for use as isolation and separation.
The interconnect from the SER to the DES typically acts like
a transmission line. Thus impedance control and ground re-
turns are an important part of system design. Impedance
should be in the 50 to 100 Ohm nominal range for the
LM2512A. Testing has been done with cables ranging from
40 to 110 Ohms without error (BER Testing). To obtain the
impedance, adjacent grounds are typically required ( 1 layer
flex), or a ground shield / layer. Total interconnect length is
intended to be in the 20cm range, however 30cm is possible
at lower data rates. Skew should be less than 500ps to max-
imize timing margins.
GROUNDING
While the LM2512A employs three separate types of ground
pins, these are intended to be connected together to a com-
mon ground plane. The separate ground pins help to isolate
switching currents from different sections of the integrated
circuit (IC). Also required is a nearby signal return (ground)
for the MPL signals. These should be provided next to the
MPL signals, as that will create the smallest current loop area.
The grounds are also useful for noise isolation and
impedance control.
PCB RECOMMENDATIONS
General guidelines for the PCB design:
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Floor plan, locate MPL SER near the connector to limit
chance of cross talk to high speed serial signals.
Route serial traces together, minimize the number of layer
changes to reduce loading.
Use ground lines as guards to minimize any noise coupling
(guarantees distance).
Avoid parallel runs with fast edge, large LVCMOS swings.
Also use a GSGSG pinout in connectors (Board to Board
or ZIF).
DES device - follow similar guidelines.
Bypass the device with MLC surface mount devices and
thinly separated power and ground planes with low
inductance feeds.
High current returns should have a separate path with a
width proportional to the amount of current carried to
minimize any resulting IR effects.
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