lm2512asnx National Semiconductor Corporation, lm2512asnx Datasheet - Page 10

• Manufacturer Part Number: lm2512asnx
• Description: Mobile Pixel Link Mpl-1 , 24-bit Rgb Display Interface Serializer With Optional Dithering And Look Up Table
• Manufacturer: National Semiconductor Corporation

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Serial Payload Parity Bit
Odd Parity is calculated on the RGB bits, control (VS, HS, and
DE) bits and F0, F1 bits and then sent from the SER to the
DES via the serial PE bit. This is included for compatibility with
certain MPL Deserializers.
Synchronization Detect and Recovery
If a data error or clock slip error occurs over the MPL link, the
RGB MPL Deserializer can detect this condition and recover
from it. The method chosen is a data transparent method, and
has very little overhead because it does not use a data ex-
pansion coding method. For the Dithered 18-bit color trans-
action, it uses two bits that are already required in the 4 MC
cycle transaction. Total overhead for each pixel is 3/24 or
12.5%.
The LM2512A MPL RGB Serializer simply increments the two
bit field F[1:0] on every pixel (MPL frame) transmitted. There-
fore every four MPL frames, the pattern will repeat. It is very
unlikely that this pattern would be found within the payload
data, and if it were found, the probability that it would repeat
for many frames becomes infinitely small. This code is used
by the MPL Deserializer to detect any frame alignment prob-
lems and quickly recover.
The RGB MPL Deserializer, upon a normal power up se-
quence, starts in the proper synchronization. If synchroniza-
FIGURE 12. 24-bit to 18-bit Dithered, 2 MD Lane (Default), RGB Transaction (NOTE MD1 and MD2)
FIGURE 11. 24-bit to 18-bit Dithered, 3 MD Lane, RGB Transaction
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tion is lost for any reason, it searches for the incrementing
pattern. Once found, it resynchronizes the output pixel data
and timing signals. See MPL DES Datasheet for details on
how the specific DES handles the Frame Sequence.
OPTIONAL DITHERING FEATURE
The LM2512A is a 2 or 3-Lane MPL Serializer, 24-bit RGB
input data (8-bits/color channel) is internally dithered to 18-
bits (6-bits/color channel) using a high-quality stochastic
dithering process. This process has a "blue noise" character-
istic that minimizes the visibility of the dither patterns. The
resulting data stream of 18-bit data is then serialized and
transmitted via MPL.
The Dither circuitry requires the VS control signal for
proper operation. This signal is used to generate a internal
signal that marks the start of the (video) frame. The serializer
samples and sends the VS information unmodified.
Dithering parameters are controled by two registers. When
the dithering is bypassed, only RGB[7:2] is serialized and
transmitted for 18-bit input RGB [5:0] (MSB aligned). RGB
[1:0] should not be connected and the unsed input should be
tied low; do not leave input open.
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