lm2507gr National Semiconductor Corporation, lm2507gr Datasheet - Page 20

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lm2507gr

Manufacturer Part Number
lm2507gr
Description
Low Power Mobile Pixel Link Mpl Level 0, 16-bit Cpu Display Interface Serializer And Deserializer
Manufacturer
National Semiconductor Corporation
Datasheet
www.national.com
Connection Diagram - LLP Package
Note: Pins are different between Master and Slave configurations.
Pin #
DAP
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
MF1 (WR
MF0 (RD
Master
CSL*
INTR
MD1
MD0
A/D
D0
D1
D2
D3
*
*
)
)
V
Mode
V
V
V
GND
M/S*
CPU
MC
TM
SSIO
DDIO
DDA
SSA
Slave
CS2*
CS1*
MD0
MD1
8-bit
D15
D14
D13
D12
IDR
NC
TABLE 4. CPU Mode Pad Assignment
TOP VIEW — (not to scale)
20
Pinl #
DAP
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Master
CS1*
CS2*
D10
D12
D13
D14
D15
CLK
D11
D4
D5
D6
D7
D8
D9
20186052
V
V
V
V
GND
DDcore
SScore
PD*
DDIO
SSIO
MF1 (WR
MF0 (RD
Slave
D10
D11
A/D
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
*
*
)
)

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