lm2507gr National Semiconductor Corporation, lm2507gr Datasheet - Page 17

• Manufacturer Part Number: lm2507gr
• Description: Low Power Mobile Pixel Link Mpl Level 0, 16-bit Cpu Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

Application Information
Power and Ground - Bumped Package
Power and ground bump assignments are shown in Figure
17. The nine center balls must be connected ground on the
FLEX CIRCUIT RECOMMENDATIONS
The three MPL lines should generally run together to mini-
mize any trace length differences (skew). For impedance
control and also noise isolation (crosstalk), guard ground
traces are recommended in between the signals. Commonly
a Ground-Signal-Ground (GSGSGSG) layout is used. Lo-
cate fast edge rate and large swing signals further away to
also minimize any coupling (unwanted crosstalk). In a
stacked flex interconnect, crosstalk also needs to be taken
into account in the above and below layers (vertical direc-
tion). To minimize any coupling locate MPL traces next to a
ground layer. Power rails also tend to generate less noise
than LVCMOS so they are also good candidates for use as
isolation and separation.
The interconnect from the Master to the Slave typically acts
like a transmission line. Thus impedance control and ground
returns are an important part of system design. Impedance
should be in the 50 to 100 Ohm nominal range for the
LM2507. Testing has been done with cables ranging from 40
to 110 Ohms without error (BER Testing). To obtain the
impedance, adjacent grounds are typically required ( 1 layer
flex), or a ground shield / layer. Total interconnect length is
intended to be in the 20cm range, however 30cm is possible
at lower data rates. Skew should be less than 500ps to
maximize timing margins.
GROUNDING
While the LM2507 employs three separate types of ground
pins, these are intended to be connected together to a
FIGURE 17. LM2507 PWR (V
(Continued)
DD
) and GND (V
17
PCB. See also, National’s Application Note AN-1126, Ball
Grid Array, for information on land pattern recommendations
and escape routing guidelines.
common ground plane. The separate ground pins help to
isolate switching currents from different sections of the inte-
grated circuit (IC). Also required is a nearby signal return
(ground) for the MPL signals. These should be provided next
to the MPL signals, as that will create the smallest current
loop area. The grounds are also useful for noise isolation
and impedance control.
PCB RECOMMENDATIONS
General guidelines for the PCB design:
• Floor plan, locate MPL Master near the connector to limit
• Route serial traces together, minimize the number of
• Use ground lines are guards to minimize any noise cou-
• Avoid parallel runs with fast edge, large LVCMOS swings.
• Also use a GSGSG pinout in connectors (Board to Board
• Slave device - follow similar guidelines.
• Bypass the device with MLC surface mount devices and
• High current returns should have a separate path with a
chance of cross talk to high speed serial signals.
layer changes to reduce loading.
pling (guarantees distance).
or ZIF).
thinly separated power and ground planes with low induc-
tance feeds.
width proportional to the amount of current carried to
minimize any resulting IR effects.
SS
) Bumps (TOP VIEW)
20186021
www.national.com