adt7476a Analog Devices, Inc., adt7476a Datasheet - Page 27

• Manufacturer Part Number: adt7476a
• Description: Dbcool Remote Thermal Controller And Voltage Monitor
• Manufacturer: Analog Devices, Inc.

When using the THERM timer, be aware of the following:
After a THERM timer read (0x79)
1.
2.
If the THERM timer is read during a THERM assertion, the
following occurs:
1.
The contents of the timer are cleared on read.
The F4P bit (Bit 5) of Interrupt Status Register 2 needs to
be cleared (assuming that the THERM timer limit has
been exceeded).
The contents of the timer are cleared.
(REG. 0x79)
(REG. 0x79)
(REG. 0x79)
THERM
THERM
THERM
THERM
THERM
THERM
TIMER
TIMER
TIMER
ACCUMULATE THERM LOW
ACCUMULATE THERM LOW
Figure 32. Understanding the THERM Timer
ASSERTION TIMES
ASSERTION TIMES
0 0 0
7 6 5
0 0 0
7 6 5
0 0 0
7 6 5
0
4
0
4
0
4
0 0 0 1
3 2 1 0
0 0 1 0
3 2 1 0
0 1 0 1
3 2 1 0
THERM LIMIT
(REG. 0x7A)
THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
THERM ASSERTED
THERM ASSERTED
2.914s
1.457s
≤ 22.76ms
≥ 45.52ms
Figure 33. Functional Block Diagram of THERM Monitoring Circuitry
0
1
2
3
4
5
6
7
COMPARATOR
Rev. 0 | Page 27 of 72
CLEARED
ON READ
7 6 5 4 3 2 1 0
IN
LATCH
RESET
2.
3.
4.
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7476A can generate SMBALERT s when a programmable
THERM timer limit has been exceeded. This allows the system
designer to ignore brief, infrequent THERM assertions, while
capturing longer THERM timer events. Register 0x7A is the
THERM timer limit register. This 8-bit register allows a limit
from 0 sec (first THERM assertion) to 5.825 sec to be set before
an SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit register.
If the THERM timer value exceeds the THERM timer limit
value, then the F4P bit (Bit 5) of Interrupt Status Register 2 is
set and an SMBALERT is generated.
Note: Depending on which pins are configured as a THERM
timer, setting the F4P bit (Bit 5) of Mask Register 2 (0x75) or Bit 0
of Mask Register 1 (0x74) masks out SMBALERT ; although the
F4P bit of Interrupt Status Register 2 is still set if the THERM
timer limit is exceeded.
Figure 33 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (0x7A) causes an SMBALERT to be
generated on the first THERM assertion. A THERM timer limit
value of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
OUT
1 = MASK
Bit 0 of the THERM timer is set to 1, because a THERM
assertion is occurring.
The THERM timer increments from zero.
If the THERM timer limit register (0x7A) = 0x00, the F4P
bit is set.
MASK REGISTER 2
STATUS REGISTER 2
F4P BIT (BIT 5)
(REG. 0x75)
F4P BIT (BIT 5)
THERM TIMER CLEARED ON READ
1.457s
182.08ms
2.914s
728.32ms
364.16ms
91.04ms
45.52ms
22.76ms
THERM TIMER
(REG. 0x79)
SMBALERT
THERM
ADT7476A