x96011 Intersil Corporation, x96011 Datasheet - Page 19

• Manufacturer Part Number: x96011
• Description: Temperature Sensor With Look Up Table Memory And Dac
• Manufacturer: Intersil Corporation

X96011 Memory Map
The X96011 contains a 80 byte array of mixed volatile
and nonvolatile memory. This array is split up into two
distinct parts, namely: (Refer to figure 12.)
– Look-up Table (LUT)
– Control and Status Registers
Figure 12. X96011 Memory Map
The Control and Status registers of the X96011 are
used in the test and setup of the device in a system.
These registers are realized as a combination of both
volatile and nonvolatile memory. These registers
reside in the memory locations 80h through 8Fh. The
reserved bits within registers 80h through 86h, must
be written as “0” if writing to them, and should be
ignored when reading. Register bits shown as 0 or 1,
in Figure 4, must be written with the indicated value if
writing to them. The reserved registers, 82h, 84h, and
from 88h through 8Fh, must not be written, and their
content should be ignored.
The LUT is realized as nonvolatile EEPROM, and
extend from memory locations 90h–CFh. This LUT is
dedicated to storing data solely for the purpose of set-
ting the outputs of Current Generators I
All bits in the LUT are preprogrammed to “0” at the
factory.
Address
CFh
8Fh
90h
80h
Control & Status
Registers
Look-up Table
(LUT)
19
OUT
64 Bytes
16 Bytes
.
Size
X96011
Addressing Protocol Overview
All Serial Interface operations must begin with a
START, followed by a Slave Address Byte. The Slave
address selects the X96011, and specifies if a Read or
Write operation is to be performed.
It should be noted that the Write Enable Latch (WEL)
bit must first be set in order to perform a Write opera-
tion to any other bit. (See “WEL: Write Enable Latch
(Volatile)” on page 13.) Also, all communication to the
X96011 over the 2-wire serial bus is conducted by
sending the MSB of each byte of data first.
The memory is physically realized as one contiguous
array, organized as 5 pages of 16 bytes each.
The X96011 2-wire protocol provides one address
byte. The next few sections explain how to access the
different areas for reading and writing.
Figure 13. Slave Address (SA) Format
Slave Address
SA7
1
SA7 - SA4
SA3 - SA1
Bit(s)
Device Type
SA0
SA6
Identifier
0
SA5
1
SA4
Device Type Identifier
Device Address
Read or Write Operation Select
0
SA3
AS2
Description
Address
Device
SA2
AS1
AS0
SA1
Read or
Write
R/W
SA0
October 25, 2005
FN8215.1