hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 5

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

Introduction
The HMP8112A is designed to decode baseband composite
or s-video NTSC and PAL signals, and convert them to either
digital YCbCr or RGB data.
The digital PLLs are designed to synchronize to all NTSC
and PAL standards. A chroma PLL is used to maintain
chroma lock for demodulation of the color information; a line-
locked PLL is used to maintain vertical spatial alignment.
The PLLs are designed to maintain lock even in the event of
VCR headswitches.
The HMP8112A contains two 8-bit A/D converters and an
I
Analog Video Inputs
The HMP8112A supports either three composite or two
composite and one S-Video input.
Three analog video inputs (LIN0, LIN1, LIN2) are used to
select which one of three composite video sources are to be
decoded. To support S-video applications, the Y channel
drives the LIN2 analog input, and the C channel drives the
CIN analog input.
The analog inputs must be AC-coupled to the video signals,
as shown in the Applications section.
Anti-Aliasing Filter
An external anti-alias filter is required to achieve optimum
performance and prevent high frequency components from
being aliased back into the video image.
For the LIN0-2 inputs, a single filter is connected to L_OUT
and L_ADIN. For CIN the anti-aliasing filter should be con-
nected to the CIN input. A recommended filter is shown
below in Figure 1.
Luminance AGC And DC RESTORE Circuits
After a
Chrominance Subcarrier Ratio Register load, the decoder
enters Acquisition Mode by attempting to lock to a new video
source. During this mode, the HAGC and DC RESTORE cir-
cuits perform continuous gain and bias adjustments until the
PLL is LOCKED onto the video signal. Once LOCKED, the
HAGC and DC RESTORE functions are performed during
programmable window periods for each horizontal video line.
The digital PLL zeroes a 10-bit pixel clock counter during
each horizontal sync tip and increments the count for each
pixel of the entire video line. The AGC amplifier attenuates or
amplifies the analog video signal during the horizontal sync
2
C port for programming internal registers
FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER
RESET
, a change of the video standard, or a PLL
332
R1
33pF
C1
8.2PH
L1
82pF
C2
R2
4.02K
HMP8112A
4-5
tip to maintain an average ADC code of 0. The DC
RESTORE circuit clamps the video signal during the back
porch to maintain an average ADC code of 64. Reference
Figure 2 for timing information and Table 5 for the recom-
mended register values to use for different video standards.
The START and END times of the HSYNC output are also
programmable and can be used as a reference for confirm-
ing proper HAGC and DC RESTORE timing.
White Peak Enable
The white peak enable input, (WPE) enables or disables the
white peak control of the luminance input. If enabled, the
AGC will reduce the gain of the video amplifier when the dig-
ital outputs exceed code 248 to prevent over-ranging the
A/D. If disabled, the AGC operates normally, keeping the hor-
izontal sync tip at code 0 and allowing the A/D’s range to go
to 255 at the maximum peak input.
Chrominance Input
The chrominance amplifier gain control is manually set by a
voltage applied to the GAIN_CNTL pin. Refer to Figure 3
below for gain characteristics. The chrominance channel
also has a digital AGC which can drive the color reference
burst to a nominal +-20 IRE. This function is enabled by
default on reset, but can be disabled using the Video Input
Control register. The chrominance input is clamped during
the DC RESTORE window to maintain an average ADC
code of 128.
VIDEO INPUT
DC RESTORE
HAGC
HSYNC
FIGURE 2. DC RESTORE AND HAGC TIMING
START
START
TIME
TIME
0
HSYNC
TIME
END
START
TIME
TIME
END
END
TIME