hmp8112acn Harris Corporation, hmp8112acn Datasheet - Page 24

• Manufacturer Part Number: hmp8112acn
• Description: Ntsc/pal Video Decoder
• Manufacturer: Harris Corporation

Pin Description
A/D TEST
CbCr[0:7]
ACTIVE
HSYNC
VSYNC
NAME
FIELD
AGND
Y[0:7]
DVLD
TEST
GND
V
V
NC
NC
CC
AA
26, 31, 37, 52,
25, 33, 35, 39,
46, 53, 62, 69,
54-58, 60, 63,
59, 68, 75, 79
15,16, 21, 22,
4, 18, 20, 32,
1, 3, 10, 11,
PQFP PIN
42, 43, 45,
NUMBER
2, 12,14
72, 80
23, 24
44, 61
73, 74
47-51
(Continued)
64
66
71
70
67
65
36
17
OUTPUT
INPUT/
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
NA
NA
CbCr Data Output Port. The chrominance data output port of the decoder. Data is in
Y Data Output Port. The luminance data output port of the decoder. Data is in un-
Data Valid. This pin signals when valid data is available on the data output ports. This
Horizontal Sync. This video synchronous pulse is generated by the detection of hor-
Active Video Flag. This flag is asserted (‘1’) when the active portion of the video line
5V Logic Supply Pins
Digital Ground Pins
Analog GND
Chrominance ADC Test Pin. This pin should be left open.
No Connect. These pins should be left open.
unsigned format and can range from 0 to 255. The CbCr data is subsampled to 4:2:2
format. In 4:2:2 format the CbCr bus toggles between Cb and Cr samples with the
first sample of a line always being Cb. The port is designed to minimize external logic
needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
signed format and can range from 16 to 255. The port is designed to minimize exter-
nal logic needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
pin is three-stated after a RESET or software reset and should be pulled high through
a 10K resistor.
izontal sync on the video input. In the absence of video, the HSYNC rate is set when
the internal PLL counters overflow. The HSYNC START and END time can be pro-
grammed. This pin is three-stated after a RESET or software reset and should be
pulled high through a 10K resistor.
Vertical Sync. This video synchronous pulse is generated by the detection of a vertical
sync on the video input. In the absence of video the VSYNC rate is set by the over flow
of the internal line rate counter. This pin is three-stated after a RESET or software reset
and should be pulled high through a 10K resistor.
Field Flag. When set (‘0’) this signals that an ODD field is presently being output from
the decoder. When cleared (‘1’) this signals an EVEN field. This flag will toggle when
no vertical sync is detected and 337 lines have elapsed. This pin is three-stated after
a RESET or software reset and should be pulled high through a 10K resistor.
is available on the output port. This signal is always set during Burst Output data
mode. This flag is free running and synchronous to CLK. This pin is three-stated after
a RESET or software reset and should be pulled high through a 10K resistor.
Test input. This pin is used for production test and should be connected to digital
ground.
5V Analog Supply Pins
Pins used as logic outputs on later decoders. Refer to HMP8115 data sheet for de-
tails.
HMP8112A
4-24
DESCRIPTION