sta323wqs STMicroelectronics, sta323wqs Datasheet - Page 54

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sta323wqs

Manufacturer Part Number
sta323wqs
Description
2.1-channel High-efficiency Digital Audio System With Qsound Qhd??
Manufacturer
STMicroelectronics
Datasheet
Register descriptions
7.12
7.12.1
7.12.2
7.12.3
7.12.4
7.12.5
54/72
Dynamics control
Limiter 1 attack/release threshold (address 0x12)
Limiter 1 attack/release threshold (address 0x13)
Limiter 2 attack/release rate (address 0x14)
Limiter 2 attack/release threshold (address 0x15)
Dynamics control description
The STA323WQS includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anti-clipping mode, or to actively reduce the dynamic range for a better listening
environment (such as a night-time listening mode, which is often needed for DVDs.) The two
modes are selected via the DRC bit in Configuration Register D, bit 5 address 0x03. Each
channel can be mapped to Limiter1 or Limiter2, or not mapped.
If a channel is not mapped, that channel will clip normally when 0 dB FS is exceeded. Each
limiter will look at the present value of each channel that is mapped to it, select the
maximum absolute value of all these channels, perform the limiting algorithm on that value,
and then, if needed, adjust the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers. When the Attack
Threshold has been exceeded, the limiter, when active, automatically starts reducing the
gain. The rate at which the gain is reduced when the attack threshold is exceeded is
dependent upon the attack rate register setting for that limiter. A peak-detect algorithms
used to control the gain reduction.
L1AT3
L2AT3
L1A3
L2A3
D7
D7
D7
D7
0
0
0
0
L1AT2
L2AT2
L1A2
L2A2
D6
D6
D6
D6
1
1
1
1
L1AT1
L2AT1
L1A1
L2A1
D5
D5
D5
D5
1
1
1
1
L1AT0
L2AT0
L1A0
L2A0
D4
D4
D4
D4
0
0
0
0
L2RT3
L1RT3
L1R3
L2R3
D3
D3
D3
D3
1
1
1
1
L2RT2
L1RT2
L1R2
L2R2
D2
D2
D2
D2
0
0
0
0
L2RT1
L1RT1
L1R1
L2R1
D1
D1
D1
D1
0
0
1
1
STA323WQS
L2RT0
L1RT0
L1R0
L2R0
D0
D0
D0
D0
0
0
1
1

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