sta002 STMicroelectronics, sta002 Datasheet - Page 22

• Manufacturer Part Number: sta002
• Description: Starmano Channel Decoder
• Manufacturer: STMicroelectronics

STA002
This register controls the Phase and frequency
detector threshold (see par. 3.4.3) and the C/N
indicator (see 3.8.2)
FLAG REGISTER
internal address: 99 H
This is a read only register when the LOCK bit is
0 then the carrier is locked. When the CNFLAG
bit is 1 then the C/N estimation is available.
4. TDM DEMULTIPLEXING
4.1 TDM_MULTIPLEX REGISTERS.
Reg name: TDM_TRSH1
Internal address: 200 H
Type: R/W
Reset Value: 4BH
Description: Master frame preamble recognition -
Synchronization threshold level.
Definition of the minimum number of TDM pre-
amble bits to be recognized before enabling the
frame synchronization.
Reg name: TDM_TRSH2
Internal address: 201 H
Type: R/W
Reset Value: 43H
Table 4: TDM FSM active states
22/43
MSB
LOCK CNFLAG
b7
X
X
X
X
0
0
1
-
X
b6
X
X
X
X
0
0
1
-
b6
b5
X
X
X
X
0
0
1
-
b5
b4
X
X
X
X
0
0
1
-
reserved
b4
b3
X
X
X
X
0
1
1
-
b2
b3
0
0
0
0
1
1
1
1
b1
X
X
X
X
0
0
0
0
b2
b0
X
X
X
X
0
1
0
1
b1
mfp_detection, mfp_presync, mfp_sync,alarm 1 (1 cycle)
mfp_detection, mfp_presync, mfp_sync,alarm 1 (2 cycle)
mfp_detection, mfp_presync, mfp_sync,alarm 1 (3 cycle)
mfp_detection, mfp_presync, mfp_sync,alarm 1 (4 cycle)
mfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (1 cycles)
mfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (2 cycles)
mfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (n cycles)
mfp_detection, mfp_presync, mfp_sync, alarm 1, alarm 2 (32 cycles)
LSB
b0
Description: Master frame preamble recognition -
Warning flag threshold level.
Definition of the minimum number of TDM pre-
amble bits to be recognized before setting an
alarm condition.
Reg name: TDM_ALARM
Internal address: 207 H
Type: R/W
Reset Value: 00H
Description: TDM finite state machine control reg-
ister (see Table 4).
Reg name: PRC_TRSH1
Internal address: 202 H
Type: R/W
Reset Value: 2AH
Description: Prime rate channel preamble recog-
nition - Synchronization threshold level.
Definition of the minimum number of PRC pre-
amble bits to be recognized before enabling PRC
synchronization.
MSB
MSB
MSB
b7
X
X
TDM FSM active states
b6
b6
X
b5
b5
b5
b4
b4
b4
b3
b3
b3
b2
b2
b2
b1
b1
b1
LSB
LSB
LSB
b0
b0
b0