mic3003 Micrel Semiconductor, mic3003 Datasheet - Page 9

• Manufacturer Part Number: mic3003
• Description: Fom Management Ic With Internal Calibration
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
May 2009
Pin Number
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TXDISABLE
Pin Name
RRSOUT/
TRSOUT
RXLOS/
VIN/INT
VMOD–
QGPO
GNDD
COMP
VBIAS
VMOD
VDDD
DATA
GPO
CLK
RS0
Pin Function
Digital input; Active high. The transmitter is disabled when this input is high or the STXDIS bit is
set to 1. The state of this input is always reflected in the TXDIS bit.
Digital I/O, open-drain, bi-directional serial data input/output.
Digital input. Serial clock input.
If bit 4 (IE) in the USRCTL register is set to 0 (its default value), this pin is configured as an analog
input. If IE bit is set to 1, this pin is configured as an open-drain output.
Analog input: Multiplexed A/D input for monitoring supply voltage, with a 0V to 5.5V input range.
Open-drain output: outputs the internally generated active-low interrupt signal /INT.
Digital input. Receiver Rate Select input. ORed with soft rate select bit SRS0 to determine the
state of the RRSOUT pin. The state of this pin is always reflected in the RS0S bit.
Ground return for digital functions.
Open-drain output. Can be selected (via OEMCFG3 bit 7) to be an open-drain GPO or an active-
low, open-drain, pulsed reset signal output controlled by the status of bits [0-2] of byte A2h: FFh.
Power supply input for digital functions.
Digital output. This programmable polarity, open-drain outputs has two purposes:
If OEMCFG6 bit 2 = 0, indicates the loss of the received signal as indicated by a level of received
optical power below the programmed RXLOS comparator threshold; may be wire-ORed with
external signals. Normal operation is indicated by a low level when OEMCFG6 bit 3 is set to 0 and
a high level when OEMCFG6 bit 3 is set to 1. RXLOS is de-asserted when VRX > LOSFLTn. The
LOS bit reflects the state of RXLOS whether driven by the MIC3003 or an external circuit.
If OEMCFG6 bit 2 = 1, TRSOUT is selected. This signal represents the transmitter rate select as
per the SFF specification. This output is controlled by the SRS1 bit ORed with the RS1 input.
Digital Output. Open-Drain or push-pull.
If OEMCFG3 bit 4 is set to 0, RRSOUT is selected. It represents the receiver rate select as per
SFF. This output is controlled by the SRS0 bit ORed with RS0 input and is open drain only.
If OEMCFG3 bit 4 is set to 1, GPO is selected. General-purpose, non-volatile output, it is
controlled by the GPO configuration bits in OEMCFG3.
Analog output. Compensation terminal for the APC loop. Connect a capacitor between this pin and
GNDA or V
Analog output. Buffered DAC output capable of sourcing or sinking up to 10mA under control of
the APC function to drive an external transistor or the APCSET pin of a laser diode driver for laser
diode DC bias. The output and feedback polarity are programmable to accommodate either an
NPN or a PNP transistor to drive a common-anode or common-cathode laser diode.
Analog input. This pin is the inverting terminal of the VMOD buffer op-amp. Connect to VMOD
(gain = 1) or a feedback resistor network to set a different gain value.
Analog Output. Buffered DAC output to set the modulation current on the laser driver IC. Operates
with either a 0– V
referenced or a V
generate a programmable current for those drivers that require a current rather than a voltage
input.
DDA
with the appropriate value to tune the APC loop time constant to a desirable value.
REF
DD
referenced programmed voltage. A simple external circuit can be used to
or a (V
DD
–V
REF
9
) – V
DD
output swing so as to generate either a ground-
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MIC3003