adm12914-2arqz-rl7 Analog Devices, Inc., adm12914-2arqz-rl7 Datasheet - Page 10

• Manufacturer Part Number: adm12914-2arqz-rl7
• Description: ?0.8% Accurate Quad Uv/ov Positive/negative Voltage Supervisor
• Manufacturer: Analog Devices, Inc.

ADM12914
MONITORING PIN CONNECTIONS
Positive Voltage Monitoring Scheme
When monitoring a positive supply, the desired nominal
operating voltage for monitoring is denoted by V
nominal current through the resistor divider, V
overvoltage trip point, and V
Figure 17 illustrates the positive voltage monitoring input connec­
tion. Three external resistors (R
voltage for monitoring (V
low-side voltage (V
corresponding VHx pin and the low-side voltage is connected
to the corresponding VLx pin. To trigger an overvoltage condition,
the low-side voltage (in this case, V
threshold on the VLx pin. The low-side voltage, V
the following equation:
Also,
Therefore, R
overvoltage monitor, is calculated using the following equation:
To trigger the undervoltage condition, the high-side voltage,
V
side voltage, V
Because R
PH
Figure 17. Positive Undervoltage/Overvoltage Monitoring Configuration
, must exceed the 0.5 V threshold on the VHx pin. The high-
V
V
R + R + R =
R
R
PL
Z
PH
Y
X
=
=
= V
= V
Z
(
(
(0.5)
(0.5)
is already known, R
V
V
Y
Z
OV
UV
, which sets the desired trip point for the
OV
UV
PH
⎛
⎜
⎜
⎝
(
⎛
⎜
⎜
⎝
(
) (
) (
V
, is given by the following equation:
V
V
V
R
R
R
R + R + R
PH
PL
I
R + R + R
I
Z
X
Y
Z
M
M
M
V
M
X
PL
X
M
)
R + R
)
)
). The high-side voltage is connected to the
)
V
Y
− R
I
R
M
M
Z
Y
Y
VHx
VLx
Z
M
) into high-side voltage (V
Z
UV
Z
Z
Y
is the undervoltage trip point.
X
⎞
⎟ = 0.5 V
⎟
⎠
⎞
⎟ = 0.5 V
⎟
⎠
, R
can be expressed as follows:
ADM12914
PL
Y
0.5V
, and R
) must exceed the 0.5 V
UVx
OVx
Z
) divide the positive
OV
M
PL
is the
, I
, is given by
M
PH
is the
,) and
Rev. PrA | Page 10 of 16
(1)
(2)
When R
formula:
If V
Negative Voltage Monitoring Scheme
Figure 18 shows the circuit configuration for negative supply
voltage monitoring. To monitor the negative voltage, a 1 V
reference voltage is required to connect to the end node of the
voltage divider circuit. This reference voltage is generated
internally and is output through the REF pin.
The equations described previously in the Positive Voltage
Monitoring Scheme section need some minor modifications for
use with negative voltage monitoring. The 1 V reference voltage
is added to the overall voltage drop; it must therefore be sub­
tracted from V
equations.
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between the 1 V reference
voltage and the negative supply voltage into high-side voltage,
V
monitoring scheme, the high-side voltage, V
the corresponding VH
connected to the corresponding VL
Monitoring Example section for further information.
THRESHOLD ACCURACY
The reset threshold accuracy is fundamental, especially at lower
voltage levels. Consider an FPGA application that requires a 1 V
core voltage input with a tolerance of ±5%, where the supply has
a specified regulation, for example, ±2.6%. As shown in Figure 19,
to ensure the supply is within the FPGA input voltage requirement
range, its voltage level must be monitored for UV and OV condi­
tions. The voltage swing on the supply itself causes the voltage
band available for setting the monitoring threshold to be quite
narrow. In this example, the threshold voltages, including the
Figure 18. Negative Undervoltage/Overvoltage Monitoring Configuration
NH
M
, and low-side voltage, V
, I
R =
X
M
Y
, V
and R
(
OV
(
V
I
, or V
M
M
M
)
Z
)
, V
V
V
− R − R
are known, R
R
NH
R
R
NL
Z
Y
X
UV
V
UV
Preliminary Technical Data
M
Z
, and V
change, each step must be recalculated.
X
pin and the low-side voltage, V
VHx
VLx
Y
REF
OV
NL
. Similar to the positive voltage
X
before using each in the previous
is calculated using the following
ADM12914
X
0.5V
pin. Refer to the Voltage
OVx
UVx
NH
, is connected to
NL
, is
(3)