adm1185armz-1 Analog Devices, Inc., adm1185armz-1 Datasheet - Page 9

• Manufacturer Part Number: adm1185armz-1
• Description: Quad Voltage Monitor And Sequencer
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION
The operation of the ADM1185 is explained in this section in
the context of the device in a voltage monitoring and sequencing
application (see Figure 18). In this application, the ADM1185
monitors four separate voltage rails, turns on three regulators in
a predefined sequence, and generates a power-good signal to
turn on a controller when all power supplies are up and stable.
POWER-ON SEQUENCING AND MONITORING
The main supply, in this case 3.3 V, powers up the device via the
VCC pin as the voltage rises. A supply voltage of 2.7 V to 5.5 V
is needed to power the device.
The VIN1 pin monitors the main 3.3 V supply. An external
resistor divider scales this voltage down for monitoring at the
VIN1 pin. The resistor ratio is chosen so that the VIN1 voltage
is 0.6 V when the main voltage rises to the preferred level at start-
up (a voltage below the nominal 3.3 V level). R1 is 4.6 kΩ and
R2 is 1.2 kΩ, so a voltage level of 2.9 V corresponds to 0.6 V on
the noninverting input of the first comparator (see Figure 17).
Table 5. Truth Table
State
1
2
3
4
5
3.3V
2.9V
0V
V
2.9V SUPPLY
GIVES 0.6V
AT VIN1 PIN
State Name
Reset
OUT1 On
OUT1, OUT2 On
OUT1, OUT2, OUT3 On
Power Good
Figure 17. Setting the Undervoltage Threshold with an
2.5V OUT
1.8V OUT
1.2V OUT
3.3V IN
t
External Resistor Divider
4.6kΩ
1.2kΩ
VIN1
0.6V
OUT1
0
1
1
1
1
ADM1185
Figure 18. Voltage Monitoring and Sequencing Application Diagram
OUT2
0
0
1
1
1
VIN1
VIN2
VIN3
VIN4
GND
ADM1185
TO LOGIC
CORE
VCC
PWRGD
POWER
GOOD
OUT1
OUT2
OUT3
OUT3
0
0
0
1
1
Rev. A | Page 9 of 16
PWRGD
0
0
0
0
1
REGULATOR 1
EN
OUT1 is an open-drain, active high output. In this application,
OUT1 is connected to the enable pin of a regulator. Before
the voltage on VIN1 reaches 0.6 V, this output is switched to
ground, disabling Regulator 1. Note that all outputs are driven
to ground as long as there is 1 V on the VCC pin of the ADM1185.
When the main system voltage reaches 2.9 V, VIN1 detects 0.6 V.
This causes OUT1 to assert after a 190 ms (typical) delay. When
this occurs, the open-drain output switches high, and the external
pull-up resistor pulls the voltage on the Regulator 1 enable pin
above its turn-on threshold, turning on the output of Regulator 1.
The assertion of OUT1 turns on Regulator 1. The 2.5 V output
of this regulator begins to rise. This is detected by Input VIN2
(with a similar resistor divider scheme, as shown in Figure 18).
When VIN2 detects the 2.5 V rail rising above its UV point, it
asserts Output OUT2, which turns on Regulator 2. A capacitor
can be placed on the VIN2 pin to slow the rise of the voltage on
this pin. This effectively sets a time delay between the 2.5 V rail
powering up and the next enabled regulator.
The same scheme is implemented with the other input and
output pins. Every rail that is turned on via an output pin,
OUTx, is monitored via an input pin VIN(x + 1).
The final comparator inside the VIN4 pin detects the final supply
turning on, which is 1.2 V in this case. The output pins, OUT1
to OUT3 are logically AND’ e d together to generate a system
power-good signal (PWRGD). There is an internal 190 ms delay
(typical) associated with the assertion of the PWRGD output.
Table 5 is a truth table that steps through the power-on sequence of
the outputs. Any associated internal time delays are also shown.
Next Event
VIN1 high for 190 ms
VIN1 and VIN2 high for 30 μs
VIN1, VIN2, and VIN3 high for 30 μs
All high for 190 ms
VIN2 , VIN3, or VIN4 low for 30 μs
GND
IN
OUT
REGULATOR 2
EN
GND
IN
OUT
REGULATOR 3
EN
GND
IN
OUT
2.5V OUT
1.8V OUT
1.2V OUT
Next State
OUT1 On
OUT1, OUT2 On
OUT1, OUT2, OUT3 On
Power Good
OUT1, OUT2, OUT3 On
ADM1185