tja1048 NXP Semiconductors, tja1048 Datasheet - Page 6

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tja1048

Manufacturer Part Number
tja1048
Description
Tja1048 Dual High-speed Can Transceiver With Standby Mode
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
TJA1048
Product data sheet
Fig 4.
Wake-up timing
t
wake(busdom)
6.2.1 TXD dominant time-out function
6.2 Fail-safe features
CANHx
CANLx
RXDx
The complete dominant-recessive-dominant pattern must be received within t
be recognized as a valid wake-up pattern (see
recessive until the wake-up event has been triggered.
After a wake-up sequence has been detected, the TJA1048 will remain in Standby mode
with the bus signals reflected on RXD1/RXD2. Note that dominant or recessive phases
lasting less than t
will not be reflected on RXD1/RXD2 in Standby mode.
A wake-up event will not be registered if any of the following events occurs while a
wake-up sequence is being transmitted:
If any of these events occurs while a wake-up sequence is being received, the internal
wake-up logic will be reset and the complete wake-up sequence will have to be
re-transmitted to trigger a wake-up event.
A 'TXD dominant time-out' timer is started when pin TXD1/TXD2 is set LOW. If the LOW
state on this pin persists for longer than t
the bus lines to recessive state. This function prevents a hardware and/or software
application failure from driving the bus lines to a permanent dominant state (blocking all
network communications). The TXD dominant time-out timer is reset when pin
TXD1/TXD2 is set HIGH. The TXD dominant time-out time also defines the minimum
possible bit rate of 40 kbit/s. The TJA1048 has two TXD dominant time-out timers that
operate independently of each other.
The TJA1048 switches to Normal mode
The complete wake-up pattern was not received within t
A V
t
IO
wake(busrec)
V
O(diff)bus
undervoltage is detected (V
All information provided in this document is subject to legal disclaimers.
fltr(wake)bus
t
wake(busdom)
Rev. 1 — 3 November 2010
will not be detected by the low-power differential receiver and
Dual high-speed CAN transceiver with Standby mode
t
to(wake)bus
IO
< V
t
fltr(wake)bus
to(dom)TXD
uvd(VIO)
Figure
; see
, the transmitter is disabled, releasing
Section
4). Pin RXD1/RXD2 will remain
to(wake)bus
6.2.3)
t
fltr(wake)bus
TJA1048
015aaa147
© NXP B.V. 2010. All rights reserved.
to(wake)bus
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