tja1042 NXP Semiconductors, tja1042 Datasheet - Page 6

• Manufacturer Part Number: tja1042
• Description: High-speed Can Transceiver With Standby Mode
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TJA1042_1
Product data sheet
6.2.1 TXD dominant time-out function
6.2.2 Bus dominant time-out function
6.2.3 Internal biasing of TXD and STB input pins
6.2.4 Undervoltage detection on pins V
6.2.5 Over-temperature protection
6.3.1 SPLIT pin
6.2 Fail-safe features
6.3 SPLIT output pin and V
A ‘TXD dominant time-out’ timer is started when pin TXD is set LOW. If the LOW state on
pin TXD persists for longer than t
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set to HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.
In Standby mode a 'bus dominant time-out' timer is started when the CAN bus changes
from recessive to dominant state. If the dominant state on the bus persists for longer than
t
(due to a bus short-circuit or a failure in one of the other nodes on the network) from
generating a permanent wake-up request. The bus dominant time-out timer is reset when
the CAN bus changes from dominant to recessive state.
Pins TXD and STB have internal pull-ups to
one or both of these pins are left floating.
Should V
will switch to Standby mode. The logic state of pin STB will be ignored until V
recovered.
Should
switch off and disengage from the bus (zero load) until V
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, T
disabled until the virtual junction temperature falls below T
recessive again. Including the TXD condition ensures that output driver oscillation due to
temperature drift is avoided.
Two versions of the TJA1042 are available, only differing in the function of a single pin. Pin
5 is either a SPLIT output pin or a V
Using the SPLIT pin on the TJA1042T in conjunction with a split termination network (see
Figure 3
reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal mode, pin SPLIT delivers a DC output voltage
of 0.5
to(dom)bus
V
V
and
IO
, the RXD pin is reset to HIGH. This function prevents a clamped dominant bus
CC
CC
drop below the
. In Standby mode or when V
drop below the V
Figure
4) can help to stabilize the recessive voltage level on the bus. This will
Rev. 01 — 9 March 2009
V
IO
CC
IO
undervoltage detection level, V
undervoltage detection level, V
supply pin
to(dom)TXD
IO
High-speed CAN transceiver with Standby mode
supply pin.
CC
CC
, the transmitter is disabled, releasing the bus
and V
V
is off, pin SPLIT is floating.
IO
to ensure a safe, defined state in case
IO
IO
j(sd)
has recovered.
j(sd)
uvd(VIO)
and TXD becomes
, the output drivers will be
uvd(VCC)
, the transceiver will
, the transceiver
© NXP B.V. 2009. All rights reserved.
TJA1042
CC
has
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