saf-xc888cm-8ffi5v Infineon Technologies Corporation, saf-xc888cm-8ffi5v Datasheet - Page 61

• Manufacturer Part Number: saf-xc888cm-8ffi5v
• Description: 8-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

Figure 11
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
3.3.2
To enhance system performance, the P-Flash banks are configured for parallel read to
allow two bytes of linear code to be read in 4 x CCLK cycles, compared to 6 x CCLK
cycles if serial read is performed. This is achieved by reading two bytes in parallel from
a P-Flash bank pair within the 3 x CCLK cycles access time and storing them in a cache.
Subsequent read from the cache by the CPU does not require a wait state and can be
completed within 1 x CCLK cycle. The result is the average instruction fetch time from
the P-Flash banks is reduced and thus, the MIPS (Mega Instruction Per Second) of the
system is increased.
However, if the parallel read feature is not desired due to certain timing constraints, it can
be disabled by calling the parallel read disable subroutine.
Data Sheet
Parallel Read Access of P-Flash
Sector 0: 3.75-Kbyte
Flash Bank Sectorization
Sector 2: 128-byte
Sector 1: 128-byte
P-Flash
54
Sector 3: 512-byte
Sector 9: 128-byte
Sector 8: 128-byte
Sector 7: 128-byte
Sector 6: 128-byte
Sector 5: 256-byte
Sector 4: 256-byte
Sector 2: 512-byte
Sector 1: 1-Kbyte
Sector 0: 1-Kbyte
D-Flash
Functional Description
XC886/888CLM
V1.1, 2009-01