saf-xc888cm-8ffi5v Infineon Technologies Corporation, saf-xc888cm-8ffi5v Datasheet - Page 139

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saf-xc888cm-8ffi5v

Manufacturer Part Number
saf-xc888cm-8ffi5v
Description
8-bit Single-chip Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet

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4.3.7
Table 51
Table 51
Parameter
SCLK clock period
MTSR delay from SCLK
MRST setup to SCLK
MRST hold from SCLK
1) T
2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Figure 52
Data Sheet
SSCmin
= T
SCLK
MTSR
MRST
provides the characteristics of the SSC timing in the XC886/888.
CPU
SSC Master Mode Timing
SSC Master Mode Timing
= 1/f
1)
SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)
1)
1)
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
CPU
. When f
t
t
CPU
Symbol
t
t
t
t
1
1
0
1
2
3
= 24 MHz,
CC
CC
SR
SR
t
2
Data
valid
t
0
t
0
= 83.3ns. T
t
min.
2*T
0
24
0
3
132
SSC
Limit Values
CPU
is the CPU clock period.
max.
8
t
1
Electrical Parameters
Unit Test
ns
ns
ns
ns
SSC_Tmg1
XC886/888CLM
Conditions
1)2)
2)
2)
2)
V1.1, 2009-01

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