sab9079hs NXP Semiconductors, sab9079hs Datasheet
sab9079hs
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sab9079hs Summary of contents
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... DATA SHEET SAB9079HS Multistandard Picture-In-Picture (PIP) controller Preliminary specification File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 2000 Jan 13 ...
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... TDA8310, TDA9143 or TDA9321H. The SAB9079HS inserts one or two live video signals with reduced sizes into the main/display video signal. All video signals are expected to be analog baseband signals. The analog signals are stripped signals without sync. ...
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... Jan 13 CONDITIONS MIN. 3.0 3.3 4.5 5.0 3.0 3.3 tbf 115 tbf 10 170 3584 HSYNC 56 1792 HSYNC 28 896 HSYNC 14 448 HSYNC 7 4 jitter during 64 s 0.7 3 Preliminary specification SAB9079HS TYP. MAX. UNIT 3.6 V 5.5 V 3.6 V tbf mA tbf mA 210 mA MHz MHz MHz MHz kHz 4 ns ...
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... DAO15 RAS SC 102 83 46 49, 50, 69, 67, 65, 61, 59, 57, 55, 53 AND VERTICAL VDRAM CONTROL FILTER AND (RE-)FORMATTING SAB9079HS AND VERTICAL TEST FILTER CONTROL 2 I C-BUS CONTROL 14, 48, 62, 76 112 111 110 97 114 115 116 ...
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... Preliminary specification SAB9079HS ...
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... V); note 2 memory write enable output (CMOS levels) memory row address strobe output (CMOS levels) memory address output bit 8 (CMOS levels) memory address output bit 7 (CMOS levels) memory address output bit 6 (CMOS levels) 6 Preliminary specification SAB9079HS ...
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... V test mode input/output (CMOS levels with hysteresis and pull-up resistor to V test mode input (CMOS levels) digital supply voltage 7 for core (3.3 V); note 3 7 Preliminary specification SAB9079HS ) ...
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... DESCRIPTION digital ground 7 for core; note 4 analog top reference for main channel ADCs analog bottom reference for main channel ADCs analog Y* input for main channel analog bias reference for main channel ADCs analog U input for main channel . DD(P) 8 Preliminary specification SAB9079HS ...
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... SSA(DA DDA(DA) 31 DAI7 32 DAI6 33 DAI5 34 DAI4 35 DAI3 36 DAI2 37 DAI1 38 2000 Jan 13 SAB9079HS Fig.2 Pin configuration. 9 Preliminary specification SAB9079HS V DDA(SF) 102 101 SV V SSA(SA) 100 V DDA(SA TSEXT 97 TSMSB 96 TSCLK 95 SVSYNC 94 SHSYNC V DDA(SP SSA(SP DDA(SH SSD(P5) ...
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... SP-Small handbook, halfpage SP-Large handbook, halfpage Twin-PIP 2000 Jan 13 handbook, halfpage MGD594 SP-Medium handbook, halfpage MGD596 handbook, halfpage MGD598 Full Field Still Full Field Live Fig.3 PIP modes. 10 Preliminary specification SAB9079HS MGD595 MGD597 DP MGD587 ...
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... Philips Semiconductors Multistandard Picture-In-Picture (PIP) controller handbook, halfpage handbook, halfpage handbook, halfpage POP-Left 2000 Jan 13 handbook, halfpage MGS388 handbook, halfpage MGS390 handbook, halfpage MGD588 Fig.4 PIP modes (continued). 11 Preliminary specification SAB9079HS MGS389 MGD589 POP-Right MGD590 POP-Double ...
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... Philips Semiconductors Multistandard Picture-In-Picture (PIP) controller handbook, halfpage MP7 handbook, halfpage Quatro handbook, halfpage MP16 2000 Jan 13 handbook, halfpage MGD591 handbook, halfpage MGD584 handbook, halfpage MGD586 Fig.5 PIP modes (continued). 12 Preliminary specification SAB9079HS MGD592 MP8 MGD585 MP9 MGL925 MP13 ...
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... Vertically it is 238 lines for NTSC and HSYNC. 286 lines for PAL. Display fine positioning 2 The I C-bus defined fine positioning has relationships to the internal HSYNC and VSYNC as illustrated in Fig.7. CIPER 720 pixels Fig.6 Acquisition fine positioning. 13 Preliminary specification SAB9079HS 228/276 lines MGS391 ...
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... Y, U and V are given by the following three equations 255 2 C-bus commands normalised (range normalised (range Preliminary specification SAB9079HS SDVFP SUB CHANNEL 238/286 lines MGS392 Y (V), Y normalised (range 128 + 127 ----------- - , 1 z – 128 ...
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... Preliminary specification SAB9079HS U – 128 128) COFACTOR 255 rv = --------- - 1 x – 254 z 255 – – --------- - -- - y 254 ...
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... LSB of the SLV byte is the R/W bit which is logic 1 in slave transmitter mode DATA data byte; this is put on the bus by SAB9079HS in an auto increment mode; if the master gives an acknowledge the next data byte is sent; if the SAB9079HS has sent all its data it starts again with the fi ...
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... OSD characters E0H to FFH reserved BUS READ REGISTERS The SAB9079HS has 8 read/status registers. The register currently used are listed in Table 8. The remaining 7 are reserved for future purposes. Reading a reserved register will return zero values. 2 Table 8 I C-bus read registers SUB ADDRESS ...
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... YUV vertical filter CTE and LTE Colour Transient Enhancement (CTE) can be set on or off. Luminance Transient Enhancement (LTE) is controllable via a scale, setting the scale value to 0H means that LTE is off. 18 Preliminary specification SAB9079HS 1 1 YUV FILTER 00H 01H 10H 11H ...
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... DATA BYTES BIT 5 BIT 4 BIT 3 2 MFreeze SFreeze I CHold MFld CTE MNonInt SNonInt Paloff Fmt411 DFilt 19 Preliminary specification SAB9079HS 720 16 then the fast blanking is BIT 2 BIT 1 BIT 0 FillSet FillOff MiS SFld ( LTE ( DPal MPal SPal Yth ( ...
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... SHDis ( SVDis ( MDHfp ( MDVfp ( MHPic ( MVPic ( PIPG PIPG PIPG 1,2 1,1 1,0 PIPG PIPG PIPG 3,2 3,1 3,0 20 Preliminary specification SAB9079HS bits make it possible to set each individual row,col BIT 3 BIT 2 BIT 1 BGVfp ( PIPG PIPG 0,3 0,2 0,1 PIPG PIPG 2,3 2,2 2,1 BIT 0 PIPG 0,0 PIPG 2,0 ...
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... DATA BYTES BIT 5 BIT 4 BIT 3 SVRed ( MVRed ( SAHfp ( SAVfp ( MAHfp ( MAVfp ( Preliminary specification SAB9079HS COLUMN 2 COLUMN 3 PIPG PIPG 0,2 PIPG PIPG 1,2 PIPG PIPG 2,2 PIPG PIPG 3,2 BIT 2 BIT 1 SHRed ( MHRed ...
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... VSPre is the number of lines before a VSYNC where the PLL is put in free-running mode. VSPost is the number of lines after the VSYNC where the PLL is still free-running. Outside this area the PLL is in normal mode. 22 Preliminary specification SAB9079HS VERTICAL MAIN SUB not valid not valid ...
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... DCha enables one step back in time (previous picture). It should be noted that if bits RepAcq and RepDisp are both logic 1 at the same time, the internal display number will be the present acquisition number minus 1. 23 Preliminary specification SAB9079HS BIT 2 BIT 1 BIT 0 SVSPol SFPol ...
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... OSDS = the background of the selected OSD character. SBSel The SBSel bits select which sub PIP has a different border colour, if SBSON is set to logic 1. The colour type can be set with SBSBrt and SBSCol. 24 Preliminary specification SAB9079HS BIT 2 BIT 1 BIT RGBOn ...
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... OSD background; the options are given in Table 20. OSDHRep and OSDVRep Bit OSDHRep (see Table 21) sets the actual number of strings per row (a maximum of 4). Bit OSDVRep sets the actual number of rows (a maximum of 4). 25 Preliminary specification SAB9079HS BIT 2 BIT 1 BIT 0 BVSize ( SBCol ( ...
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... DATA BYTES BIT 5 BIT 4 BIT 3 OSDChr 0,0,0 OSDChr 0,0,1 OSDChr 0,0,2 OSDChr 0,0,3 OSDChr 0,1,0 OSDChr 0,1,1 OSDChr 0,1,2 OSDChr 0,1,3 | OSDChr 5,3,2 OSDChr 5,3,3 26 Preliminary specification SAB9079HS BIT 2 BIT 1 OSDVRep ( NOTE x PIP (BG) 0 30% white 1 50% PIP/30% white OSDVRep NR. OF ROWS BIT 2 BIT 1 BIT pos,row,col BIT 0 ...
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... Preliminary specification SAB9079HS < = > ...
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... Philips Semiconductors Multistandard Picture-In-Picture (PIP) controller handbook, full pagewidth UPPER 3 BITS 2000 Jan 13 LOWER 4 BITS Fig.8 OSD character set. 28 Preliminary specification SAB9079HS MGS828 FH ...
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... BYCoef1 ( BUCoef1 ( BVCoef1 ( RYCoef2 ( RUCoef2 ( RVCoef2 ( GYCoef2 ( GUCoef2 ( GVCoef2 ( BYCoef2 ( BUCoef2 ( BVCoef2 ( Preliminary specification SAB9079HS 128) 128) 128) coef < 2. For PAL pictures BIT 3 BIT 2 BIT 1 BIT 0 RGBOn ...
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... SVClDel ( SYClPer SUClPer SVClPer SFidPos ( SVGATE MYClDel ( MUClDel ( MVClDel ( MYClPer MUClPer MVClPer MFidPos ( MVGATE TGAct1 TGAct2 TColBar 30 Preliminary specification SAB9079HS BIT 2 BIT 1 BIT TGenY TGenU TGenV ...
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... The PLL generates, from the HSYNC, an internal system clock of 3584 HSYNC which is approximately 56 MHz. The other system clocks are derived from this clock. They are in the range 3584, 1792, 896 or 448 CONDITIONS note 1 note 2 PARAMETER in free air 31 Preliminary specification SAB9079HS HSYNC. MIN. MAX. 0.5 +6.0 V 0.5 +4.0 V 0.5 +4 ...
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... Jan unless otherwise specified. amb CONDITIONS note 1 note 2 note 2 note 3 note 4 note 4 note 5 note 5 note 5 clamping off clamping on; note 2 note 6 note 2 note 2 note 2 32 Preliminary specification SAB9079HS MIN. TYPE MAX. 4.5 5.0 5.5 3.0 3.3 3.6 3.0 3.3 3 100 0 100 0 50 0.4 0.4 ...
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... are made by a resistor division of V ref(T)(nom) DDA(nom) of the ADCs, which is derived from pin V Vref(B)(SA/MA Vref(T)(SA/MA) Vref(B)(SA/MA) 33 Preliminary specification SAB9079HS MIN. TYPE MAX. 1.25 1.35 1.45 1.80 1.95 2.10 1.10 1.20 1.30 0.15 0.22 0.30 1 1000 0 50 1792HSYNC 896HSYNC ...
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... U ADC mismatch ADC(U) MM analog V ADC mismatch ADC(V) MM analog YUV ADC mismatch ADC(YUV) Note 1. Mismatch = (max min)/average. 2000 Jan 13 CONDITIONS MIN. 0.20 0.20 0.15 0.15 0.19 0.19 6.0 6.0 6.0 note 1 note 1 note 1 note 1 34 Preliminary specification SAB9079HS TYP. MAX. UNIT 0.22 0.24 LSB/mV 0.22 0.24 LSB/mV 0.17 0.19 LSB/mV 0.17 0.19 LSB/mV 0.21 0.23 LSB/mV 0.21 0.23 LSB/mV 6.8 7.5 LSB/mV 6.8 7.5 LSB/mV 6.8 7 ...
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... C; unless otherwise specified. CONDITIONS MIN DDD( 3.6 V DDD V = 3.6 V DDD 23 note 1 Y*UV Y*UV/RGB SUB HV FBL Y*UV MAIN AND HV DISPLAY SWITCH HV 35 Preliminary specification SAB9079HS TYPE MAX 0.4 0.4 0 3584xHSYNC Y*UV FEATURE BOX HV MGS829 UNIT %V DDD %V DDD ...
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... Sample rate of 14 Mhz, 720 Y* pixels/line Horizontal reduction factors Vertical reduction factors FORMAT FORMAT yes no; note 1 yes FORMAT FORMAT yes yes yes no; note 1 yes no; note 1 36 Preliminary specification SAB9079HS and and ...
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... BIT 4 BIT 3 ABMode CTE (1:0) D2FH YUVFilter 0 00H 0 01H 0 10H 0 11H 1 xxH 1 xxH 1 xxH 1 xxH 1 00H 1 00H 1 00H 1 00H 37 Preliminary specification SAB9079HS BIT 2 BIT 1 MFld SFld (1:0) (1:0) LTE (2:0) D2FV ABMode 00H 0 00H 0 00H 0 00H 0 00H 0 01H 0 10H 0 11H 1 00H 1 01H 1 10H 1 11H ...
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... H DESIGN RESTRICTIONS The design has margins for a 2Fh frequency of 31.5 kHz. Applying a SVGA source with a horizontal frequency of 38 kHz will stress the SAB9079HS. Therefore, a SVGA source can only be applied under the following restricted conditions: Power supply spread of 5% instead of 10% No VCR like phase jump in 2Fh signal. ...
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... In this application there is no relationship between the deflection and acquisition circuits. A double window feature can be realized by letting the feature box compress one window and make the second window by the SAB9079HS. In this application the HVSYNC of the feature box/line doubler is connected to the main acquisition HVSYNC. The restriction is that no main PIPs can be displayed ...
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... In the master mode the SAB9079HS generates the HSYNC and VSYNC for display/deflection. There is no protection built in. HSYNC and VSYNC cannot be coupled directly to a tube. A deflection IC should be applied ...
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... The resolution of the BGVfp bits changes in 2Fh and xFv modes. In 2Fh and 1Fv modes the vertical resolution is 2 lines/field/step on 1Fh base. In 2Fh and 2Fv modes the vertical resolution is 2 lines/field/step on 2Fh base. 41 Preliminary specification SAB9079HS BIT 3 BIT 2 BIT 1 MFld SFld ...
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... FIELDS FOR MAIN FIELDS FOR SUB CHANNEL CHANNEL Preliminary specification SAB9079HS D2FV ABMode 00H 0 00H 0 00H 0 00H 0 00H 0 01H 0 10H 0 11H 1 00H 1 01H 1 10H 1 11H REMARKS 3 except for horizontal ...
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... EATURE BOX APPLICATION Z In this mode the SAB9079HS generates the display clock which is derived from the main clock and synchronization signals. The whole system runs at one PLL. Only full screen images of the main decoder are handled. The PIP insertion of the sub channel is not required here; see Fig.11. ...
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... Jan scale (1) ( 0.23 20.1 14.1 23.35 17.35 1.60 0.50 0.11 19.9 13.9 23.05 17.05 REFERENCES JEDEC EIAJ 44 Preliminary specification SAB9079HS detail 1.03 7 0.20 0.08 0.08 0.73 0 EUROPEAN ISSUE DATE PROJECTION 98-03-27 SOT387 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 45 Preliminary specification SAB9079HS ...
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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Jan 13 SOLDERING METHOD WAVE not suitable (2) suitable (3)(4) not recommended (5) not recommended 46 Preliminary specification SAB9079HS (1) REFLOW suitable suitable suitable suitable suitable ...
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... I Philips. This specification can be ordered using the code 9398 393 40011. 2000 Jan components conveys a license under the Philips’ system provided the system conforms to the I 47 Preliminary specification SAB9079HS 2 C patent to use the 2 C specification defined by ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...