sab9075h NXP Semiconductors, sab9075h Datasheet - Page 29

• Manufacturer Part Number: sab9075h
• Description: Picture-in-picture Pip Controller For Ntsc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
External memory
For the external memory two VDRAMS of type Mitsubishi
M5442256 are used. They have a storage capacity of
262144 words of 4-bit each and will be used in parallel.
An overview of the timing to the VDRAM is depicted in
Fig.19. Three different timing modes are shown. If the
SAB9075 is not in one of these three modes, it is in idle
mode in which all the control signals are HIGH. An idle
mode takes at least 4 clock periods. Switching from one
mode to another is always carried out via this idle mode.
The clock signal shown is an internal clock derived from
the PLLs and is approximately 27 MHz.
Main and sub-ADCs
Both main and sub-channels convert the analog input
signals to digital signals by three ADCs for each channel.
The input levels of the ADCs are equal and can set by the
MAV
reference levels are made internally by a resistor network
which divides the analog V
signal levels of 1.5 V. If the application requires a different
set of levels the internal resistors can be shunted. External
capacitors are required to filter AC components on the
reference levels.
The resolution of the ADCs is 6-bit and the sampling is
carried out at the system frequency of 27 MHz. The
bias current I
decreased.
The inputs should be AC-coupled and an internal clamping
circuit will clamp the input to MAV
luminance channels and to
for the chrominance channels. The clamping starts at the
active edge of the burstkey.
For more information see chapter “Test and application
information”.
February 1995
MAV
---------------------------------------------------- -
SAV
-------------------------------------------------- -
Picture-in-Picture (PIP) controller for NTSC
refT
refT
refT
, SAV
+
2
+
2
SAV
MAV
bias
refT
refB
is made internally but can be increased or
, MAV
refB
+
+
LSB
----------- -
LSB
----------- -
refB
2
2
, and SAV
DD
to a default set of preferred
refB
refB
and SAV
pins.The
refB
for the
29
Output DACs
The digital processed signals are converted to analog
signals by means of three DACs. The output voltages of
these DACs are default set by the DAV
DAV
1.5 V. The output buffer after each DAC is a PMOS source
follower.
For more information see chapter “Test and application
information”.
HUE and SAT DACs
The HUE and SAT DACs are resistor DACs based on a
R2R network. They have a direct control from their I
register and therefore their sample frequency is limited by
the I
I
PLLs and clock generation
The SAB9075H has two PLLs on-board, one for the sub-
channel and one for the main-channel and the display part.
The PLLs lock to the input signals MH
internal clock frequency is 1 728 times higher which is
approximately 27 MHz in a standard NTSC system.
The positive edges of the H
timing points. For good short term stability they have to be
noise/jitter free.
2
CV
2
refTY
DD
C-bus frequency. The output voltage is linear with the
. Therefore the V
pins for the TOP-levels. Default signal levels are
DD
of this block is a separate pin.
sync
signals are the driving
Preliminary specification
sync
SAB9075H
refTU
and SH
, DAV
sync
refTV
2
C-bus
. The
and