adm8513 Infineon Technologies Corporation, adm8513 Datasheet - Page 68

• Manufacturer Part Number: adm8513
• Description: Usb-to-10/100 Mbps Ethernet Lan Controller
• Manufacturer: Infineon Technologies Corporation

2. Reset the registers to their default values. Note that this does not affect registers 20, 22, 30 or 31. These
LoopbackLoop back of transmit data to receive via a path as closed to the wire as possible. When set inhibits
actual transmission on the wire.
Speed SelectionForces speed of Phy only when auto-negotiation is disabled. The default state of this bit will be
determined by a power-up configuration pin in this case. Otherwise it defaults to 1.
Auto-neg EnableDefaults to pin programmed value. When cleared allows forcing of speed and duplex settings.
When set (after being cleared) causes re-start of auto-neg process. Pin programming at power-up allows it to
come up disabled and for software to write the desired capability before allowing the first negotiation to commence.
Restart NegotiationOnly has effect when auto-negotiating. Restarts state machine.
Power DownHas no effect in this device. Test mode power down modes may be implemented in other specific
modules.
IsolatePuts RMII receive signals into high impedance state and ignores transmit signals.
Duplex ModeWhen bit12 is cleared (i.e. autoneg disabled), this bit forces full duplex (bit = 1) or half duplex (bit =
0).
Collision TestAlways 0 because collision signal is not implemented.
Status
STA
Status
Field
100T4
100FD
100HD
10FD
Data Sheet
registers are not reset by this bit to allow test configurations to be written and then not affected by resetting the
port.
Note: No reset is performed to analogue sections of the port. There is also no physical reset to any internal
clock synthesisers or the local clock recovery oscillator which will continue to run throughout the reset period.
However since the port is restarted and autoneg re-run the process of locking the frequency of the local
oscillator (slave) to the reference oscillator (master) will be repeated as it is at the start of any link initialization
process.
Bits
15
14
13
12
Type
ro
ro
ro
ro
Description
100 BASE T4
Not supported
100BASE-X Full Duplex
0
1
100BASE-X Half Duplex
0
1
10 Mbit/s Full Duplex
0
1
B
B
B
B
B
B
100FDN, PHY is not 100BASE-X full duplex capable
100FD, PHY is 100BASE-X full duplex capable
100HDN, PHY is not 100BASE-X half duplex capable
100HD, PHY is 100BASE-X half duplex capable
10FDN, PHY is not 10 Mbit/s Full duplex capable
10FD, PHY is 10 Mbit/s Full duplex capable
Offset
68
1
H
Registers Description
Rev. 1.21, 2005-12-05
Data Sheet
Reset Value
ADM8513
7849
H