adm708san Analog Devices, Inc., adm708san Datasheet - Page 9

• Manufacturer Part Number: adm708san
• Description: 3 V, Voltage Monitoring Microprocessor Supervisory Circuit
• Manufacturer: Analog Devices, Inc.

CIRCUIT INFORMATION
POWER-FAIL
POWER-FAIL RESET
The reset output provides a reset ( RESET or RESET) output
signal to the microprocessor whenever the V
the reset threshold. The actual reset threshold voltage is
dependent on whether a P, R, S, or T suffix device is used. An
internal timer holds the reset output active for 200 ms after the
voltage on V
power-on reset signal for the microprocessor. It allows time for
both the power supply and the microprocessor to stabilize after
power-up. If a power supply brownout or interruption occurs,
the reset line is similarly activated and remains active for
200 ms after the supply recovers. If another interruption occurs
during an active reset period, the reset timeout period
continues for an additional 200 ms.
The reset output is guaranteed to remain valid with V
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
The ADM706P provides an active high RESET signal; the
ADM706R/ADM706S/ADM706T provide an active low RESET
signal; and the ADM708R/ADM706S/ADM706T provide both
RESET and RESET .
POWER-FAIL
WATCHDOG
INPUT (WDI)
INPUT (PFI)
INPUT (PFI)
V
V
MR
MR
CC
CC
* VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
CC
V
1.25V
Figure 13. ADM706 Functional Block Diagram
Figure 14. ADM708 Functional Block Diagram
1.25V
V
REF
REF
TRANSITION
WATCHDOG
V
rises above the threshold. This is intended as a
DETECTOR
V
CC
*
*
CC
70μA
70μA
ADM706P/ADM706R/
ADM706S/ADM706T
ADM708R/ADM708S/
GENERATOR
GENERATOR
WATCHDOG
RESET AND
WATCHDOG
TIMEBASE
RESET
RESET
TIMER
ADM708T
CC
input is below
WATCHDOG
OUTPUT (WDO)
POWER-FAIL
OUTPUT (PFO)
RESET,
(P = RESET)
RESET
RESET
POWER-FAIL
OUTPUT (PFO)
CC
as low
Rev. B | Page 9 of 16
MANUAL RESET
The MR input allows other reset sources, such as a manual reset
switch, to generate a processor reset. The input is effectively
debounced by the timeout period (200 ms typical). The MR
input is TTL-/CMOS-compatible; it can also be driven by any
logic reset output. If unused, the MR input can be tied high or
left floating.
RESET
WATCHDOG TIMER (ADM706x)
The watchdog timer circuit can be used to monitor the activity
of the microprocessor to check that it is not stalled in an
indefinite loop. An output line on the processor is used to
toggle the watchdog input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output ( WDO ) is
driven low. The WDO output can be connected to a nonmaskable
interrupt (NMI) on the processor. Therefore, if the watchdog
timer times out, an interrupt is generated. The interrupt service
routine should then be used to rectify the problem.
The watchdog timer is cleared by either a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/ RESET going
active. Therefore, the watchdog timeout period begins after
reset goes inactive.
When V
whether or not the watchdog timer has timed out. Normally,
this generates an interrupt, but it is overridden by RESET/ RESET
going active.
WDO
V
MR
CC
CC
falls below the reset threshold, WDO is forced low
V
NOTES
RESET = COMPLEMENT OF RESET
RT
Figure 15. RESET , MR , and WDO Timing
V
RT
t
RS
MR EXTERNALLY
DRIVEN LOW
t
RS