adm708san Analog Devices, Inc., adm708san Datasheet - Page 6

• Manufacturer Part Number: adm708san
• Description: 3 V, Voltage Monitoring Microprocessor Supervisory Circuit
• Manufacturer: Analog Devices, Inc.

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Mnemonic
MR
V
GND
PFI
PFO
WDI
NC
RESET
RESET
WDO
CC
GND
V
MR
PFI
CC
1
2
3
4
(Not to Scale)
ADM706P
Figure 3. ADM706P
TOP VIEW
ADM706P/
ADM706R/
ADM706S/
ADM706T
1
2
3
4
5
6
N/A
7
(ADM706R/
ADM706S/
ADM706T Only)
7
(ADM706P Only)
8
8
5
7
6
WDO
RESET
WDI
PFO
Pin No.
ADM708R/
ADM708S/
ADM708T
1
2
3
4
5
N/A
6
7
8
N/A
Description
Manual Reset Input. When taken below 0.6 V a RESET is generated. MR can be driven from
TTL, CMOS logic or from a manual reset switch as it is internally debounced. An internal 70
μA pull-up current holds the input high when floating.
Power Supply Input.
Ground reference for all signals (0 V).
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less
than 1.25 V, PFO goes low. If unused, PFI should be connected to GND.
Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI
is less than 1.25 V.
Watchdog Input. WDI is a 3-level input. If WDI remains either high or low for longer than the
watchdog timeout period, the watchdog output WDO goes low. The timer resets with each
transition at the WDI input. Either a high-to-low or a low-to-high transition clears the
counter. The internal timer is also cleared whenever reset is asserted. The watchdog timer is
disabled when WDI is left floating or connected to a three-state buffer.
No Connect.
Logic Output. RESET goes low for 200 ms when triggered. It can be triggered either by V
being below the reset threshold or by a low signal on the MR input. RESET remains low
whenever V
the reset threshold or MR goes from low to high. A watchdog timeout does not trigger
RESET unless WDO is connected to MR.
Logic Output. RESET is an active high output suitable for systems that use active high RESET
logic. It is the inverse of RESET.
Logic Output/Watchdog Output. WDO goes low if the internal watchdog timer times out as
a result of inactivity on the WDI input. It remains low until the watchdog timer is cleared.
WDO also goes low during low line conditions. Whenever V
WDO remains low. As soon as V
immediately.
Figure 4. ADM706R/ADM706S/ADM706T
GND
V
MR
PFI
CC
1
2
3
4
CC
(Not to Scale)
ADM706R/
Rev. B | Page 6 of 16
ADM706S/
ADM706T
is below the reset threshold. It remains low for 200 ms after V
TOP VIEW
8
6
5
7
WDO
RESET
WDI
PFO
CC
goes above the reset threshold, WDO goes high
Figure 5. ADM708R/ADM708S/ADM708T
GND
V
MR
PFI
CC
CC
1
2
3
4
NC = NO CONNECT
is below the reset threshold,
(Not to Scale)
ADM708R/
ADM708S/
ADM708T
TOP VIEW
8
7
6
5
CC
RESET
RESET
NC
PFO
goes above
CC