m66252fp Mitsumi Electronics, Corp., m66252fp Datasheet

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m66252fp

Manufacturer Part Number
m66252fp
Description
1152 X 8-bit Line Memory Fifo
Manufacturer
Mitsumi Electronics, Corp.
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M66252FP
Manufacturer:
MIT
Quantity:
20 000
Part Number:
m66252fp-200D
Manufacturer:
STM
Quantity:
7 355
DESCRIPTION
The M66252P/FP is a high-speed line memory with a FIFO
(First In First Out) structure of 1152-word 8-bit configuration
which uses high-performance silicon gate CMOS process
technology.
It has separate clock, enable and reset signals for write and
read and is most suitable as a buffer memory between
devices with different data processing throughput.
FEATURES
• Memory construction ........................................................
• High-speed cycle ............................................ 50ns (min.)
• High-speed access ........................................ 40ns (max.)
• Output hold ....................................................... 5ns (min.)
• Fully independent, asynchronous write and read opera-
• Variable-length delay bit
• Output .................................................................... 3-state
APPLICATION
Digital photocopiers, high-speed facsimiles, laser beam print-
ers.
BLOCK DIAGRAM
tions
Write
enable input
Write
reset input
Write
clock input
............................. 1152words x 8bits (dynamic memory)
WRES
WCK
Vcc
WE
19
17
18
20
D
24 23 22 21 16 15 14 13
0
D
1
D
Input buffer
Data input
2
D
3
D
4
D
5
D
6
(1152 x 8 bits)
Memory array
D
7
Q
1 2 3 4 9 10 11 12
Read enable input
PIN CONFIGURATION (TOP VIEW)
0
Read reset input
Read clock input
Data output
Data output
Q
1
Q
Output buffer
Data output
2
Q
3
Q
RRES
4
GND
RCK
Q
RE
Q
Q
Q
Q
Q
Q
Q
Q
5
0
1
2
3
4
5
6
7
Q
1152 x 8-BIT LINE MEMORY (FIFO)
6
Outline
Q
M66252P/FP
10
11
12
MITSUBISHI DIGITAL ASSP
1
3
4
5
6
9
2
7
8
7
1152 x 8-BIT LINE MEMORY (FIFO)
MITSUBISHI DIGITAL ASSP
24P4Y
24P2W-A
16
24
23
22
21
20
19
18
17
15
14
13
M66252P/FP
5
6
8
7
D
D
D
D
WE
WRES
V
WCK
D
D
D
D
RE
RRES
GND
RCK
0
1
2
3
CC
4
5
6
7
Read
enable input
Read
clock input
Data input
Write enable input
Write reset input
Write clock input
Data input
Read
reset input
1

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m66252fp Summary of contents

Page 1

DESCRIPTION The M66252P/ high-speed line memory with a FIFO (First In First Out) structure of 1152-word 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read ...

Page 2

FUNCTION When the status of write enable input WE is “L,” data on D thru D are written on the memory synchronously with write 7 clock input WCK rise edges. At this time, write address counter executes counting. The following ...

Page 3

SWITCHING CHARACTERISTICS (T = – Symbol t Access time AC t Output hold time OH t Output enable time OEN t Output disable time ODIS TIMING CHARACTERISTICS (T = – ...

Page 4

TEST CIRCUIT 30pF : t L Input pulse level Input pulse rise time and fall time: 3ns Measurement reference level, input: 1.3V Measurement reference level, output: 1.3V (Note: t Load capacitance C includes floating ...

Page 5

TIMING CHARTS • Write Cycles Cycle n Cycle(n+1) WCK WCK WCKH WCKL (n) Dn • Write Reset Cycles Cycle(n–1) Cycle n WCK WCK NRESH RESS WRES ...

Page 6

Matters that needs attention when WCK stops n cycle n+1 cycle WCK t WCK ( Period for writing data (n) into memory Input data of n cycle is read at the rising ...

Page 7

Read Cycles Cycle n Cycle(n+1) RCK RCK RCKH RCKL RE Qn (n) • Read Reset Cycles Cycle(n–1) Cycle n RCK RCK NRESH RESS RRES Qn (n–1) Cycle(n+2) Disable cycles ...

Page 8

VARIABLE-LENGTH DELAY BITS • 1-line (1152-bit) delay A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge of ...

Page 9

WRES and RRES at a cycle corresponding to delay length) Cycle 0(W) Cycle 1(W) Cycle 2(W) WCK RCK t t RESS RESH WRES RRES (0) (1) Qn • n-bit delay ...

Page 10

Shortest read of data “n” written in cycle n Cycle n–1 on read side should be started after end of cycle n+1 on write side When the start of cycle n–1 on read side is earlier than the end ...

Page 11

APPLICATION EXAMPLE Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction. M66252 Line (n+1) image data 1-line delay M66252 1-line delay Primary scanning direction ...

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