w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 81

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

20.3 PS/2 Status Registers (PS2STS)
Bit 6: START_DEC START BIT DETECT
Bit 5: XMIT_TIMEOUT
Bit 0: PS2_T/R - PS/2 Channel Transmit/Receive (default = 0).
Advance address
Bit 7: Reserved.
1 = Transmit data.
0 = Receive data
This bit is set on detecting start bit of receive condition.
The START_DEC bit is cleared when the Status Register is read.
This bit will be set on either of 3 transmit conditions occurred, and then PS2 control logic will
generate a 300us LOW pulse on CLK line following assertion of the XMIT_TIMEOUT bit. The
PS2_T/R bit is also cleared.
1: When the transmitter bit time (time between falling edges) exceeds 300us.
2: When the transmitter start bit is not received within 25ms from signaling a transmit start
3: If the time from the 1st (start) bit to the 10th (parity) bit exceeds 2ms.
If RDATA_RDY=1, set PS2_T/R bit will result in PS2 control logic floats DATA line and
drives CLK line LOW until a read of Receive Register.
If the PS2_T/R bit is set while the channel is under receiving data before the falling edge of
the 10th (parity bit) clock, the received data is discarded and RDATA_RDY won’t be set.
And if not, the received data is stored in the Receive Register and RDATA_RDY is set.
If RDATA_RDY=0, clear PS2_T/R bit will floats both CLK and DATA line and waiting for the
auxiliary device sending data in.
event.
This bit is only valid when PS2_EN=1.
This bit should be set before a data write to Transmit Register. Otherwise, the written data
will be ignored.
After setting the PS2_T/R bit, the PS2 control logic will drive CLK line to LOW and then
float the DATA line until a data written to the Transmit Register or until the PS2_T/R bit is
cleared.
After writing on the Transmit Register to invoke a transmission, the PS2 control logic
drives the data line low and, within 80ns, floats the clock line to signal auxiliary device that
a data expects to transmit is now available.
The PS2_T/R bit is cleared on the 11th clock edge of the transmission or if a Transmit
Timeout error condition occurs.
0x12, 0 x 16, 0 x 1A
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W83L950D