w83l950d Winbond Electronics Corp America, w83l950d Datasheet - Page 80

• Manufacturer Part Number: w83l950d
• Description: Peripheral Personal Computer Keyboard Controller
• Manufacturer: Winbond Electronics Corp America

20.2 PS/2 Control Registers (PS2CON)
Bit 5-4: STOP
Bit 3-2: PARITY
Bit 1: PS2_EN - PS2 Channel Enable (Default = 0).
Bit 6: Inhibit bit
Advance address 0 x 11, 0 x 15, 0 x 19)
Bit 7: NOISE FILTER ENABLE
0: Disable noise filter for clock line
1: Enable noise filter for clock line
Note: Turn ON this switch may NOT need to add the capacitor on PS2 line.
The LOW to HIGH transition of Inhibit bit generates a 100us LOW pulse on PS2 CLK line.
This operation is logical OR’ed with PS2 internal CLK LOW control logic. This is an optional
operation which be used for the firmware expects to prevent the PS2 line contention.
Bits [5:4] of the Control Register are used to set the level of the stop bit expected by the
PS/2 channel state machine.
These bits are only valid when PS2_EN=1.
Bits [5:4]
= 00: Receiver expects an active high stop bit.
= 01: Receiver expects an active low stop bit.
= 10: Receiver ignores the level of the Stop bit (11th bit is not interpreted as a
= 11: Reserved.
Bits [3:2] of the Control Register are used to set the parity expected by the PS/2 channel
state machine. These bits are therefore only valid when PS2_EN=1.
Bits [3:2]
= 00: Receiver expects Odd Parity (default).
= 01: Receiver expects Even Parity.
= 10: Receiver ignores level of the parity bit (10th bit is not interpreted as a
= 11: Reserved.
Set this bit to enable the PS/2 hardware control logic.
If the PS2_EN bit is cleared while the PS2 is under receiving data before the falling edge of
the 10th (parity bit) clock, the received data is discarded and RDATA_RDY won’ t be set.
And if not, the data is stored in the Receive Register and RDATA_RDY is set, also the parity
error flag will not be set.
stop bit).
parity bit).
- 71 -
Publication Release Date: June 23, 2003
W83L950D
Revision 1.0