saf1761 NXP Semiconductors, saf1761 Datasheet - Page 139
saf1761
Manufacturer Part Number
saf1761
Description
Hi-speed Universal Serial Bus On-the-go Controller
Manufacturer
NXP Semiconductors
Datasheet
1.SAF1761.pdf
(166 pages)
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NXP Semiconductors
SAF1761_1
Product data sheet
Fig 25. SAF1761 register access timing: separate address and data buses (8051 style)
(write) DATA[31:0]
(read) DATA[31:0]
AD[17:1]
15.2.1.1 PIO register read or write
WR_N
CS_N
RD_N
15.2.1 PIO timing
15.2 Peripheral timing
Table 176. PIO register read or write
T
Symbol Parameter
V
Reading
t
t
t
t
t
t
t
Writing
t
t
t
t
t
t
w18
su18
h18
d18
d28
d38
d48
w28
su28
h28
su38
h38
d58
amb
CC(I/O)
= 40 C to +85 C; unless otherwise specified.
= 1.65 V to 1.95 V
t
t
su18
d48
t
t
d68
su28
RD_N LOW pulse width
address set-up time before RD_N LOW
address hold time after RD_N HIGH
RD_N LOW to data valid delay
RD_N HIGH to data outputs 3-state delay
RD_N HIGH to CS_N HIGH delay
CS_N LOW to RD_N LOW delay
WR_N LOW pulse width
address set-up time before WR_N LOW
address hold time after WR_N HIGH
data set-up time before WR_N HIGH
data hold time after WR_N HIGH
WR_N HIGH to CS_N HIGH delay
t
d18
Rev. 01 — 18 November 2009
t
w28
t
w18
t
su38
t
h38
t
d58
t
h28
t
t
d38
h18
t
d28
Min
> t
0
0
-
-
0
0
15
0
0
5
2
1
Hi-Speed USB OTG controller
d18
Max
-
-
-
33
1
-
-
-
-
-
-
-
-
SAF1761
© NXP B.V. 2009. All rights reserved.
004aaa529
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