lan9215 Standard Microsystems Corp., lan9215 Datasheet - Page 20

• Manufacturer Part Number: lan9215
• Description: Lan9215 16-bit Non-pci 10/100 Ethernet Controller With Hp Auto-mdix Support
• Manufacturer: Standard Microsystems Corp.

Revision 2.3 (08-06-08)
Internal Regulator
Activity Indicator),
General Purpose
+3.3V I/O Power
Analog Ground
nLED1 (Speed
nLED2 (Link &
nLED3 (Full-
+3.3V Analog
Core Voltage
Core Ground
I/O Ground
Decoupling
Indicator
Indicator),
I/O data,
Test Pin
Duplex
RBIAS
NAME
Power
Power
).
GND_CORE
VDD_CORE
GPIO[2:0]/
nLED[3:1]
SYMBOL
GND_IO
VDD_IO
ATEST
RBIAS
VDD_A
VSS_A
VREG
Table 2.5 System and Power Signals (continued)
BUFFER
IS/O12/
TYPE
OD12
AI
P
P
P
P
P
P
P
I
DATASHEET
20
NUM
PINS
3
1
1
1
8
8
3
4
2
2
General Purpose I/O data: These three
general-purpose signals are fully programmable
as either push-pull output, open-drain output or
input by writing the GPIO_CFG configuration
register in the CSR’s. They are also multiplexed
as GP LED connections.
GPIO signals are Schmitt-triggered inputs.
When configured as LED outputs these signals
are open-drain.
nLED1 (Speed Indicator). This signal is driven
low when the operating speed is 100Mbs,
during auto-negotiation and when the cable is
disconnected. This signal is driven high only
during 10Mbs operation.
nLED2 (Link & Activity Indicator). This signal
is driven low (LED on) when the LAN9215
detects a valid link. This signal is pulsed high
(LED off) for 80mS whenever transmit or
receive activity is detected. This signal is then
driven low again for a minimum of 80mS, after
which time it will repeat the process if TX or RX
activity is detected. Effectively, LED2 is
activated solid for a link. When transmit or
receive activity is sensed LED2 will flash as an
activity indicator.
nLED3 (Full-Duplex Indicator). This signal is
driven low when the link is operating in full-
duplex mode.
PLL Bias: Connect to an external 12.0K ohm
1.0% resistor to ground. Used for the PLL Bias
circuit.
This pin must be connected to VDD for normal
operation.
3.3V input for internal voltage regulator
+3.3V I/O logic power supply pins
Ground for I/O pins
(100-TQFP Package Only)
+3.3V analog power supply pins. See
Ground for analog circuitry
(100-TQFP Package Only)
+1.8 V from internal core regulator. Both pins
must be connected together externally. Each
pin requires a 0.01uF decoupling capacitor. In
addition, pin 3 requires a bulk 10uF capacitor
(<2 Ohm ESR) in parallel. These pins must not
be used to supply power to other external
devices. See
Ground for internal digital logic
(100-TQFP Package Only)
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX Support
Note
DESCRIPTION
2.1.
SMSC LAN9215
Note
Datasheet
2.1.