lan8700 Standard Microsystems Corp., lan8700 Datasheet - Page 15

• Manufacturer Part Number: lan8700
• Description: ?15kv Esd Protected Mii/rmii 10/100 Ethernet Transceiver With Hp Auto-mdix Support And Flexpwrtm Technology In A Small Footprint
• Manufacturer: Standard Microsystems Corp.

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
SIGNAL NAME
SIGNAL NAME
SPEED100/
FDUPLEX/
ACTIVITY/
PHYAD4
PHYAD3
PHYAD2
PHYAD1
PHYAD0
CRS_DV
MODE2
MODE1
MODE0
RXD2/
RXD1/
RXD0/
MDIO
LINK/
CRS/
RMII/
MDC
COL/
Table 3.4 Boot Strap Configuration Inputs
TYPE
TYPE
Table 3.3 Management Signals
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
DATASHEET
Management Data Input/OUTPUT: Serial management data
input/output.
Management Clock: Serial management clock.
PHY Address Bit 4: set the default address of the PHY. This
signal is mux’d with CRS
Note:
PHY Address Bit 3: set the default address of the PHY.
Note:
PHY Address Bit 2: set the default address of the PHY.
Note:
PHY Address Bit 1: set the default address of the PHY.
Note:
PHY Address Bit 0: set the default address of the PHY.
Note:
PHY Operating Mode Bit 2: set the default MODE of the PHY.
See
the MODE options.
Note:
PHY Operating Mode Bit 1: set the default MODE of the PHY.
See
the MODE options.
Note:
PHY Operating Mode Bit 0: set the default MODE of the PHY.
See
the MODE options.
Note:
Digital Communication Mode: set the digital communications
mode of the PHY to RMII or MII. This signal is muxed with the
Collision signal (MII mode) and Carrier Sense/ receive Data Valid
(RMII mode)
Float for MII mode.
Pull up with a resistor to VDDIO for RMII mode (see
“Boot Strapping Configuration Resistors,” on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
TM
15
Technology in a Small Footprint
This signal is mux’d with CRS
This signal is mux’d with FDUPLEX
This signal is mux’d with ACTIVITY
This signal is mux’d with LINK
This signal is mux’d with SPEED100
This signal is mux’d with RXD2
This signal is mux’d with RXD1
This signal is mux’d with RXD0
DESCRIPTION
DESCRIPTION
(Note
3.1)
Revision 2.0 (07-15-08)
32) .
Table 4.3,
52, for
52, for
52, for