mc33291l Freescale Semiconductor, Inc, mc33291l Datasheet - Page 13

• Manufacturer Part Number: mc33291l
• Description: Eight-output Switch With Serial Peripheral Interface I/o
• Manufacturer: Freescale Semiconductor, Inc

CHIP SELECT (CS)
CS
transferred from the MCU to the 33291L by way of the SI pin
and from the 33291L to the MCU through the SO pin.
Clocked-in data from the MCU is transferred from the 33291L
Shift register and latched into the power outputs on the rising
edge of the
drain status information is transferred from the power outputs
then loaded into the Shift register of the device. The
also controls the output driver of the serial output (SO) pin.
Whenever the
output driver is enabled allowing information to be transferred
from the 33291L to the MCU. To avoid data corruption or the
generation of spurious data, it is essential the high-to-low
transition of the
low state.
SYSTEM CLOCK (SCLK)
registers of the 33291L. The serial input (SI) pin accepts data
into the Input Shift register on the falling edge of the SCLK
signal while the serial output (SO) pin shifts data information
out of the SO line driver on the rising edge of the SCLK signal.
False clocking of the Shift register must be avoided to
guarantee validity of data. It is essential the SCLK pin be in a
logic low state whenever the chip select bar (
any transition. For this reason, it is recommended, though not
Analog Integrated Circuit Device Data
Freescale Semiconductor
The 33291L receives its MCU communication through the
The system clock (SCLK) pin clocks the internal shift
pin. Whenever this pin is in a logic low state, data can be
CS
CS
signal. On the falling edge of the
CS
pin goes to a logic low state, the SO pin
signal occur only when SCLK is in a logic
V
V
DD
DD
FUNCTIONAL PIN DESCRIPTION
Figure 15. Multiple MCU SPI Control
Microcontroller
Microcontroller
CS
B0
B1
SS
(Alternate Master)
B0
B1
SS
8-Bit
8-Bit
MC68XX
(Master)
MC68XX
) pin makes
CS
Parallel
Parallel
Ports
Ports
SPI
SPI
signal,
CS
SCLK
MISO
MOSI
SCLK
MISO
MOSI
A0
A1
A2
A0
A1
A2
pin
absolutely necessary, the SCLK pin be kept in a low logic
state as long as the device is not accessed (
state). When
and SI pins are ignored and SO is tri-stated (high
impedance). See the Data Transfer Timing diagram in
Figure
SERIAL INSTRUCTION (SI)
read on the falling edge of SCLK. A logic high state present
on this pin when the SCLK signal rises will program a specific
output OFF. In turn,
the rising edge of the
present on the SI pin will program the output ON, In turn, the
pin turns ON the specific output on the rising edge of the
signal.
8-bit serial stream of data is required to be synchronously
entered into the SI pin starting with Output 7, followed by
Output 6, Output 5, and so on, to Output 0. Referring to
Figure
corresponding to Output 7. For each rise of the SCLK signal,
with
OFF) is synchronously loaded into the Shift register per the
data-bit SI state. The Shift register is full after eight bits of
information have been entered. To preserve data integrity,
care should be taken to not transition SI as SCLK transitions
from a low-to-high logic state.
This pin is for the input of serial instruction (SI) data. SI is
To program the eight outputs of the 33291L ON or OFF, an
CS
17, page 16.
17, the DO bit is the most significant bit (MSB)
held in a logic low state, a data-bit instruction (ON or
CS
SCLK
SO
SI
CS
SCLK
SO
SI
CS
SCLK
SO
SI
33291
33291
33291
8-Bit
8-Bit
8-Bit
CS
is in a logic high state, signals at the SCLK
CS
8 Outputs
8 Outputs
8 Outputs
CS
pin turns OFF the specific output on
signal. Conversely, a logic low state
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
CS
in logic high
33291L
CS
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