sja1000t-n1 NXP Semiconductors, sja1000t-n1 Datasheet - Page 30

• Manufacturer Part Number: sja1000t-n1
• Description: Stand-alone Can Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. When the transmit error counter exceeds the limit of 255, the bus status bit is set to logic 1 (bus-off), the
2. Errors detected during reception or transmission will effect the error counters according to the CAN 2.0B protocol
3. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle. If both bits are set the
4. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit or the self
5. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is logic 0 (locked), the written byte
6. When a message that is to be received has passed the acceptance filter successfully, the CAN controller needs
7. After reading all messages within the RXFIFO and releasing their memory space with the command release receive
2000 Jan 04
SR.1
SR.0
Stand-alone CAN controller
CAN controller will set the reset mode bit to logic 1 (present) and an error warning interrupt is generated, if enabled.
The transmit error counter is set to 127 and the receive error counter is cleared. It will stay in this mode until the CPU
clears the reset mode bit. Once this is completed the CAN controller will wait the minimum protocol-defined time
(128 occurrences of the bus-free signal) counting down the transmit error counter. After that the bus status bit is
cleared (bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error warning interrupt
is generated, if enabled. Reading the TX error counter during this time gives information about the status of the
bus-off recovery.
specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU
warning limit (EWLR). An error warning interrupt is generated, if enabled. The default value of EWLR after hardware
reset is 96.
controller is waiting to become idle again. After a hardware reset 11 consecutive recessive bits have to be detected
until the idle status is reached. After bus-off this will take 128 of 11 consecutive recessive bits.
reception request bit is set to logic 1. The transmission complete status bit will remain at logic 0 until a message is
transmitted successfully.
will not be accepted and will be lost without this being indicated.
space in the RXFIFO to store the message descriptor and for each data byte which has been received. If there is not
enough space to store the message, that message is dropped and the data overrun condition is indicated to the CPU
at the moment this message becomes valid. If this message is not completed successfully (e.g. due to an error), no
overrun condition is indicated.
buffer this bit is cleared.
BIT
DOS
RBS
SYMBOL
Data Overrun Status;
note 6
Receive Buffer Status;
note 7
NAME
VALUE
30
1
0
1
0
overrun; a message was lost because there was
not enough space for that message in the RXFIFO
absent; no data overrun has occurred since the
last clear data overrun command was given
full; one or more complete messages are available
in the RXFIFO
empty; no message is available
FUNCTION
Product specification
SJA1000