isp1506a NXP Semiconductors, isp1506a Datasheet - Page 33

• Manufacturer Part Number: isp1506a
• Description: Isp1506a; Isp1506b Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 17.
ISP1506A_ISP1506B_1
Product data sheet
Packet sequence High-speed
Transmit-Transmit
(host only)
Receive-Transmit
(host or
peripheral)
Receive-Receive
(peripheral only)
Transmit-Receive
(host or
peripheral)
Fig 13. High-speed transmit-to-transmit packet timing
CLOCK
DATA
DP or
DIR
[3:0]
NXT
STP
DM
D
N 1
Link decision times
D
N
link delay
15 to 24
1 to 14
1
92
DATA
TX end delay (two to five clocks)
Full-speed
link delay
7 to 18
7 to 18
1
80
EOP
Low-speed
link delay
77 to 247
77 to 247
1
718
Rev. 01 — 30 May 2007
link decision time (15 to 24 clocks)
USB interpacket delay (88 to 192 high-speed bit times)
Definition
Number of clocks a host link must wait before driving the
TXCMD for the second packet.
In high-speed, the link starts counting from the assertion of
STP for the first packet.
In full-speed, the link starts counting from the RXCMD,
indicating LINESTATE has changed from SE0 to J for the
first packet. The timing given ensures inter-packet delays of
2 bit times to 6.5 bit times.
Number of clocks the link must wait before driving the
TXCMD for the transmit packet.
In high-speed, the link starts counting from the end of the
receive packet; de-assertion of DIR or an RXCMD
indicating RxActive is LOW.
In full-speed or low-speed, the link starts counting from the
RXCMD, indicating LINESTATE has changed from SE0 to J
for the receive packet. The timing given ensures
inter-packet delays of 2 bit times to 6.5 bit times.
Minimum number of clocks between consecutive receive
packets. The link must be able to receive both packets.
Host or peripheral transmits a packet and will time-out after
this amount of clock cycles if a response is not received.
Any subsequent transmission can occur after this time.
ISP1506A; ISP1506B
IDLE
ULPI HS USB OTG transceiver
(one to two clocks)
TXCMD
© NXP B.V. 2007. All rights reserved.
TX start delay
SYNC
D0
004aaa891
33 of 79
D1