isp1504a1 NXP Semiconductors, isp1504a1 Datasheet - Page 76

• Manufacturer Part Number: isp1504a1
• Description: Isp1504a1; Isp1504c1 Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
23. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
Table 11. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .27
Table 12. LINESTATE[1:0] encoding for upstream
Table 13. LINESTATE[1:0] encoding for downstream
Table 14. Encoded V
Table 15. V
Table 16. Encoded USB event signals . . . . . . . . . . . . . .30
Table 17. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .34
Table 18. Link decision times . . . . . . . . . . . . . . . . . . . . .35
Table 19. Immediate register set overview . . . . . . . . . . .47
Table 20. Extended register set overview . . . . . . . . . . . .47
Table 21. Vendor ID Low register (address R = 00h)
Table 22. Vendor ID High register (address R = 01h)
Table 23. Product ID Low register (address R = 02h)
Table 24. Product ID High register (address R = 03h)
Table 25. Function Control register (address R = 04h to
Table 26. Function Control register (address
Table 27. Interface Control register (address R = 07h to
Table 28. Interface Control register (address R = 07h to
Table 29. OTG Control register (address R = 0Ah to
Table 30. OTG Control register (address R = 0Ah to
ISP1504A1_ISP1504C1_1
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended V
ULPI signal description . . . . . . . . . . . . . . . . . .14
Signal mapping during low-power mode . . . . .16
Signal mapping for 6-pin serial mode . . . . . . .16
Signal mapping for 3-pin serial mode . . . . . . .17
Operating states and corresponding resistor
settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
OTG Control register power control bits . . . . .25
facing ports: peripheral . . . . . . . . . . . . . . . . . .27
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .28
typical applications . . . . . . . . . . . . . . . . . . . . . .29
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
06h, W = 04h, S = 05h, C = 06h) bit allocation 48
R = 04h to 06h, W = 04h, S = 05h, C = 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .49
09h, W = 07h, S = 08h, C = 09h) bit allocation 49
09h, W = 07h, S = 08h, C = 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
BUS
indicators in RXCMD required for
BUS
voltage state . . . . . . . . . . . . . .28
BUS
capacitor value . . . . . . .12
Rev. 01 — 6 August 2007
Table 31. USB Interrupt Enable Rising Edge register
Table 32. USB Interrupt Enable Rising Edge register
Table 33. USB Interrupt Enable Falling Edge register
Table 34. USB Interrupt Enable Falling Edge register
Table 35. USB Interrupt Status register (address R =
Table 36. USB Interrupt Status register (address R =
Table 37. USB Interrupt Latch register (address R =
Table 38. USB Interrupt Latch register (address R =
Table 39. Debug register (address R = 15h) bit
Table 40. Debug register (address R = 15h) bit
Table 41. Scratch register (address R = 16h to 18h,
Table 42. Power Control register (address R = 3Dh to
Table 43. Power Control register (address R = 3Dh to
Table 44. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 45. Recommended operating conditions . . . . . . . . 56
Table 46. Static characteristics: supply pins . . . . . . . . . . 57
Table 47. Static characteristics: digital pins CLOCK,
Table 48. Static characteristics: digital pin FAULT . . . . . 58
Table 49. Static characteristics: digital pin PSW_N . . . . 58
Table 50. Static characteristics: analog I/O pins DP,
Table 51. Static characteristics: analog pin V
Table 52. Static characteristics: ID detection circuit . . . . 60
Table 53. Static characteristics: resistor reference . . . . . 60
Table 54. Dynamic characteristics: reset and clock . . . . 61
Table 55. Dynamic characteristics: digital I/O pins . . . . . 62
Table 56. Dynamic characteristics: other characteristics 62
ISP1504A1; ISP1504C1
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,
C = 0Fh) bit allocation . . . . . . . . . . . . . . . . . . . 51
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,
C = 0Fh) bit description . . . . . . . . . . . . . . . . . . 52
(address R = 10h to 12h, W = 10h, S = 11h,
C = 12h) bit allocation . . . . . . . . . . . . . . . . . . . 52
(address R = 10h to 12h, W = 10h, S = 11h,
C = 12h) bit description . . . . . . . . . . . . . . . . . . 52
13h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 53
13h) bit description . . . . . . . . . . . . . . . . . . . . . 53
14h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 53
14h) bit description . . . . . . . . . . . . . . . . . . . . . 53
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
W = 16h, S = 17h, C = 18h) bit description . . . 54
3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DIR, STP, NXT, DATA[7:0], RESET_N,
CS_N/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . 57
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ULPI HS USB OTG transceiver
© NXP B.V. 2007. All rights reserved.
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BUS
. . . . . . 60
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