isp1160 NXP Semiconductors, isp1160 Datasheet - Page 43
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isp1160
Manufacturer Part Number
isp1160
Description
Isp1160 Embedded Universal Serial Bus Host Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1160.pdf
(88 pages)
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Philips Semiconductors
Table 18:
9397 750 13963
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptDisable register: bit allocation
R/W
R/W
R/W
MIE
31
23
15
0
0
0
10.1.6 HcInterruptDisable register (R/W: 05H/85H)
Table 17:
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
writing a logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned.
Code (Hex): 05 — read
Code (Hex): 85 — write
Bit
31
30 to 7
6
5
4
3
2
1
0
R/W
R/W
R/W
30
22
14
0
0
0
HcInterruptEnable register: bit description
Symbol
MIE
-
RHSC
FNO
UE
RD
SF
-
SO
R/W
R/W
R/W
29
21
13
0
0
0
Rev. 05 — 24 December 2004
Description
MasterInterruptEnable by the HCD: A logic 0 is ignored by the
HC. A logic 1 enables interrupt generation by events specified in
other bits of this register.
reserved
0 — ignore
1 — enable interrupt generation due to Root Hub Status Change
0 — ignore
1 — enable interrupt generation due to frame Number Overflow
0 — ignore
1 — enable interrupt generation due to Unrecoverable Error
0 — ignore
1 — enable interrupt generation due to Resume Detect
0 — ignore
1 — enable interrupt generation due to Start of frame
reserved
0 — ignore
1 — enable interrupt generation due to Scheduling Overrun
R/W
R/W
R/W
28
20
12
0
0
0
reserved
reserved
reserved
R/W
R/W
R/W
27
19
11
0
0
0
Embedded USB Host Controller
R/W
R/W
R/W
26
18
10
0
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
R/W
R/W
R/W
25
17
0
0
9
0
ISP1160
R/W
R/W
R/W
24
16
0
0
8
0
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