isp1109 NXP Semiconductors, isp1109 Datasheet - Page 28

• Manufacturer Part Number: isp1109
• Description: Universal Serial Bus Transceiver With Carkit Support
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13355
Product data sheet
9.3.1 Pinout description
9.3.2 Interface overview
9.3.3 Interface protocol description
9.3 SPI interface
The SPI interface consists of four signals as given in
Table 37:
The SPI interface has the following characteristics:
The SPI port is configured to use 32-bit serial data words, using 1 bit for R/W, 5 bits for
address, 1 bit for null, and 25 bits for data.
For each SPI transfer, a one is written to pin SPI_MOSI, if this SPI transfer is to be a write.
A zero is written to the pin, if this is to be a read-only command. If a zero is written, then
any data sent after the address bits is ignored and the internal contents of the field
addressed do not change when the 32
written to pin SPI_MOSI MSB first. Finally, data bits are written to the pin MSB first. Once
all the data bits are written, data is transferred to the actual registers on the 32
SPI_CLK. SPI_CS must go LOW and return to HIGH to start the next SPI data transfer.
Pin name
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_CS
•
•
•
•
•
•
•
•
•
•
The maximum clock rate is 26 MHz.
Data is transmitted, most significant bit first. Each data field consists of a total of
32 bits.
The data and SPI_CLK signals are ignored, if SPI_CS is LOW. SPI_MISO is set to
three-state, if SPI_CS is programmed LOW.
SPI_CS is active (HIGH) only during the serial data transmission.
All input data is sampled at the rising edge of the SPI_CLK signal. Any transition on
SPI_MOSI must occur at least 5 ns before the rising edge of SPI_CLK and remain
stable for at least 5 ns after the rising edge of SPI_CLK.
All output data is updated at the rising edge of the SPI_CLK signal. Any transition on
SPI_MISO must occur at least 5 ns before the rising edge of SPI_CLK and remain
stable for at least 19.23 ns after the rising edge of SPI_CLK.
SPI_CS must be active (HIGH) at least 5 ns before the rising edge of the first
SPI_CLK signal, and must remain active (HIGH) at least 61.5 ns after the last falling
edge of SPI_CLK.
Coincident rising or falling edge of SPI_CLK and SPI_CS are not allowed.
If SPI_CS goes LOW before enough bits are sent, then the data bits sent are ignored.
When SPI_CS goes LOW to complete the SPI operation, the next rising edge of
SPI_CS must be delayed by at least 30 ns.
SPI interface pin description
Rev. 01 — 14 July 2005
Description
serial data input line
serial data output line
clock input line
clock enable line (active HIGH)
nd
SPI_CLK is sent. Next, the 5-bit address is
USB transceiver with carkit support
Table
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
37.
ISP1109
nd
28 of 59