ucb1100 NXP Semiconductors, ucb1100 Datasheet - Page 26

• Manufacturer Part Number: ucb1100
• Description: Advanced Modem/audio Analog Front-end
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6.7.3 Control Register Data Transfer
The last 16 bits of the UCB1100 word is made up of control register
data. The selection of the control register and whether it is read or
written is defined by the control register address field [bit 17:20] and
the “write” bit [bit 21]. For a read action on the a control register, the
control register address field has to set to the desired control
register address and the “write” bit has to be set to zero in the
SIBDin stream, The read data is sent by the UCB1100 within the
control register data field of SIBDout during the same frame as the
read request occurred. In addition, during a read cycle, the control
register data field of SIBDin is ignored by the UCB1100 which
implies that no modifications of the UCB1100 settings can be
performed when the “write” bit equals zero in the SIBDin
data-stream.
For a write cycle (“write” bit = 1), the control register data contents of
SIBDin are written to the UCB1100 register selected by the register
address field after receipt of the complete first word (the update is
performed during the 64th bit in the SIB frame). This implies that the
1998 May 08
Advanced modem/audio analog front-end
sibsync
sibdout
sibdin
sibclk
control data
sibsync
sibdin
sibclk
bit 63
tsclsy
Figure 30. Control Register Update Timing
Figure 31. Timing Definitions SIB Interface
tsibclk
bit 64
thclsy
26
control register data contents of SIBDout data-stream in a SIB frame
represents the previous contents of the selected control register.
The control register address in the sibdout data-stream is a copy of
the selected control register in the sibdin data-stream. These bits
show an additional delay since they pass additional circuitry in the
UCB1100.
The control register data is actually written in the control registers
after the transfer of the first sib word is completed. This implies that
the control register data is updated during bit 64 of the sib frame.
The control data is only updated when the write bit is ‘1’ in the sib
frame. The control data will not be updated when the write bit equals
‘0’. This simplifies the read out of control register data, since it is not
required to send ‘valid’ data in the control register data field when a
control register is read, if the write bit is kept at ‘0’.
The control register data in the sibdout stream is sampled just
before the sib frame is started. This implies that the returned control
register data represents the ‘old’ control data, in case new data was
provided in the sibdin data stream.
tpcldo
tpcdu
tscldi
bit 65
thcldi
bit 66
Preliminary specification
UCB1100
SN00155
tpdido
SN00156