adv601lc Analog Devices, Inc., adv601lc Datasheet - Page 29

• Manufacturer Part Number: adv601lc
• Description: Ultralow Cost Video Codec
• Manufacturer: Analog Devices, Inc.

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Using the ADV601LC In Standalone Applications
Figure 14 shows the ADV601LC in a noncomputer based appli-
cations. Here, an ADSP-21csp01 digital signal processor pro-
vides Host control and BW calculation services. Note that all
control and BW operations occur over the host interface in this
design.
Connecting the ADV601LC to Popular Video Decoders and
Encoders
The following circuits are recommendations only. Analog
Devices has not actually built or tested these circuits.
Using the Philips SAA7111 Video Decoder
The SAA7111 example circuit, which appears in Figure 15, is
used in this configuration on the ADV601LC Video Lab dem-
onstration board.
Using the Analog Devices ADV7175 Video Encoder
Because the ADV7175 has a CCIR-656 interface, it connects
directly with the ADV601LC without “glue” logic. Note that
the ADV7175 can only be used at CCIR-601 sampling rates.
The ADV7175 example circuit, which appears in Figure 16, is
used in this configuration on the ADV601LC Video Lab dem-
onstration board.
Figure 15. ADV601LC and SAA7111 Example Interfac-
ing Block Diagram
SAA7111
XTAL
XTAL
THE ADSP-21csp01 INTERNAL CLOCK RATE
DOUBLE THE INPUT CLOCK
*THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL
CLOCK RATE, RANGING FROM 12 TO 21MHz
ADSP-21csp01
Y(0:7)
LLC
DATA8-15
DATA0–7
IOACK
CLKIN
ADR2
ADR1
FLIN2
FLIN0
FLIN1
ADR0
IOMS
IRQ0
WR
RD
Figure 14. Alternate Standalone Application Design
VCLK
VDATA (0:7)
(CCIR-656 MODE)
ADV601LC
FIFO_ERR
ACK
ADR0
ADR1
DQ0–DQ7
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
CS
RD
WR
STATS_R
HIRQ
LCODE
BE0–BE1
BE2–BE3
VCLKO*
FIFO_SRQ
FIFO_STP
ADV601LC
–29–
VDATA [0–7]
Using the Raytheon TMC22173 Video Decoder
Raytheon has a whole family of video parts. Any member of the
family can be used. The user must select the part needed based
on the requirements of the application. Because the Raytheon
part does not include the A/Ds, an external A/D is necessary in
this design (or a pair of A/Ds for S video).
The part can be used in CCIR-656 (D1) mode for a zero con-
trol signal interface. Special attention must be paid to the video
output modes in order to get the right data to the right pins (see
the following diagram).
Note that the circuit in Figure 17 has not been built or tested.
Figure 17. ADV601LC and TMC22153 Example CCIR-656
Mode Interface
Figure 16. ADV601LC and ADV7175 Example Interfac-
ing Block Diagram
D0–D15
A0–A8
VCLK
RAS
CAS
WE
(MODE 0 & SLAVE MODE)
ADV7175
XTAL
27MHz PAL OR NTSC
TOSHIBA TC514265DJ/DZ/DFT-60
NEC
NEC
HITACHI
ANY DRAM USED WITH THE ADV601LC
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
TMC22153
MODE SET TO:
CDEC = 1
YUVT = 1
F422
= X
HM514265CJ-60
CLOCK
BLANK
P7–P0
CLOCK
PD424210ALE-60
PD42S4210ALE-60
ALSB
Y(2:9)
COMPOSITE VIDEO INPUT
LLC
Y[0–7]
OE
A0–A8
DQ1–DQ16
RAS
CAS
WEL
WEH
VCLK
10k
150
(256K
24.576MHz
SAA7111
XTAL
XTAL
DRAM
16-BIT)
(CCIR656 & SLAVE MODE)
VCLKO
VDATA (7:0)
VCLK
VDATA (0:7)
(CCIR-656 MODE)
XTAL
ADV601LC
ADV601LC
XTAL
ADV601LC
VCLK