adv601lc Analog Devices, Inc., adv601lc Datasheet
adv601lc
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adv601lc Summary of contents
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... ADV601LC offers you many application-specific advantages. A review of the Gen- eral Theory of Operation and Applying the ADV601LC sections will help you get the most use out of the ADV601LC in any given application. The ADV601LC accepts component digital video through the Video Interface and outputs a compressed bit stream though the Host Interface in Encode Mode ...
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... ADV601LC REGISTER DESCRIPTIONS . . . . . . . . . . . . 10 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 16 Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DRAM Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Compressed Data-Stream Definition . . . . . . . . . . . . . . . . 22 APPLYING THE ADV601LC . . . . . . . . . . . . . . . . . . . . . . 28 Using the ADV601LC in Computer Applications . . . . . . 28 Using the ADV601LC in Stand-Alone Applications . . . . 29 Connecting the ADV601LC to Popular Video Decoders and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 GETTING THE MOST OUT OF ADV601LC . . . . . . . . . 30 ADV601LC SPECIFICATIONS ...
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... The quantization and entropy encoding processes provide the ADV601LC’s data compression. The wavelet theory, on which the ADV601LC is based new mathematical apparatus first explicitly introduced by Morlet and Grossman in their works on geophysics during the mid 80s. ...
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... High quality filtered/decimated images can be extracted/created without computational overhead. Through leverage of these key points, the ADV601LC not only compresses video, but offers a host of application features. Please see the Applying the ADV601LC section for details on getting the most out of the ADV601LC’s sub-band coding architecture in different applications BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128 ...
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... Figure 4. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts) REV. 0 Figure 5. Modified Mallat Diagram of Image –5– ADV601LC ...
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... ADV601LC LUMINANCE AND COLOR COMPONENTS (EACH SEPARATELY) HIGH LOW PASS IN PASS HIGH LOW PASS IN PASS IN BLOCK HIGH LOW HIGH PASS IN PASS IN PASS BLOCK BLOCK BLOCK HIGH PASS BLOCK ...
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... Mallat block data and (2) levels of quantization range widely from high to low frequency block. (Note that the fill is based on a log formula.) The relation between actual ADV601LC bin width factors and the Mallat block fill pattern in Figure 8 appears in Table II ...
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... Widths during decode because the Bin Width is stored in the 0x011a compressed image during encode. 0x0066 0x0066 PROGRAMMER’S MODEL 0x0055 A host device configures the ADV601LC using the Host I/O 0x0054 Port. The host reads from status registers and writes to control 0x0054 registers through the Host I/O Port. 0x0054 0x0054 Table IV ...
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... INDIRECT REGISTER ADDRESS AND INDIRECT REGISTER DATA REGISTERS} *NOTE: YOU MUST WRITE 0X0880 TO THE MODE CONTROL REGISTER ON CHIP RESET TO SELECT THE CORRECT PIXEL MODE Figure 9. Map of ADV601LC Direct and Indirect Registers REV. 0 DIRECT (EXTERNALLY ACCESSIBLE) REGISTERS BYTE 2 BYTE 1 INDIRECT REGISTER ADDRESS ...
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... Interrupt Mask / Status Register Direct (Read/Write) Register Byte Offset 0x0C This 16-bit register contains interrupt mask and status bits that control the state of the ADV601LC’s HIRQ pin. With the seven mask bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR); select the conditions that are ORed together to determine the output of the HIRQ pin ...
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... Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can be caused by a defective DRAM, the inability of the Host to keep up with the ADV601LC compressed data stream, or bit errors in the data stream. Note that the ADV601LC recovers from this condition without host intervention. ...
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... Normal operation 1 Software Reset. This bit is set on hardware reset and must be cleared before the ADV601LC can begin processing. (reset value) When this bit is set during encode, the ADV601LC completes processing the current field then suspends operation until the SWR bit is cleared. When this bit is set during decode, the ADV601LC suspends operation immediately and does not resume operation until the SWR bit is cleared ...
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... Indirect (Write Only) Register Index 0x05 This register holds the setting for the vertical end of the ADV601LC’s active video area. If the value is larger than the max size of the selected video mode, the ADV601LC uses the max size of the selected mode for VEND. ...
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... These registers let the Host or DSP read sum of squares statistics from the ADV601LC; using these values (with the Sum of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV601LC indi- cates that the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin. Read the statistics at any time ...
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... Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are 6.10, unsigned, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries) (undefined at reset). [15:0] Bin Width Values, BW[15:0] [15:0] Reciprocal Bin Width Values, RBW[15:0] REV. 0 –15– ADV601LC ...
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... Mode). The pin operates as follows: • Output (Master) HI during Field1 lines of video and LO otherwise • Input (Slave this input indicates Field1 lines of video Encode or Decode. This output pin indicates the coding mode of the ADV601LC and operates as follows: • LO Decode Mode (Video Interface is output) • ...
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... DRAM Row Address Strobe. This pin is compatible with 30 pF loads. DRAM Column Address Strobe. This pin is compatible with 30 pF loads. DRAM Write Enable. This pin is compatible with 30 pF loads. Note that the ADV601LC does not have a DRAM OE pin. Tie the DRAM’s OE pin to ground. Description Host Data Bus ...
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... Mode Control register. ADV601LC Chip Reset. Asserting this pin returns all registers to reset state. Note that the ADV601LC must be reset at least once after power-up with this active low signal input. For more information on reset, see the SWR bit description. ...
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... In CCIR-656 mode, this control is set to Uni- polar, since the color components are offset by 128. Note that it is likely the ADV601LC will function if this control is in the wrong state, but compression performance will be degraded important to set this bit correctly. ...
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... CCIR-656 physical interface. Electrically, CCIR-656 specifies differential ECL levels to be used for all interfaces. The ADV601LC, however, only supports unipolar, TTL logic thresholds. Systems designs that interface to strictly conforming CCIR-656 devices (especially when inter- facing over long cable distances) must include ECL level shifters and line drivers ...
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... The DRAM manager manages the entire operation and refresh of the DRAM. The interface between the ADV601LC DRAM manager and DRAM is designed to be transparent to the user. The ADV601LC DRAM pins should be connected to the DRAM as called out in the Pin Function Descriptions section. The ADV601LC re- quires one 256K word by 16-bit DRAM ...
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... Through its Host Interface the ADV601LC outputs (during encode) and receives (during decode) compressed digital video data. This stream of data passing between the ADV601LC and the host is hierarchically structured and broken up into blocks of data as shown in Figure 11. Table IV shows pseudo code for a ...
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... Block Sequence: #SOB1, #SOB2, #SOB3, #SOB4 or #SOB5 <BW> <Huff_Data> REV. 0 “Frame N; Field 1” “Frame N; Field 2” “Frame N+1; Field 1” “Frame N+1; Field 2” “Frame N+M; Field 1” “Frame N+M; Field 2” “Required in decode to let the ADV601LC know the sequence of fields is complete.” –23– ADV601LC ...
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... A pseudo code bit stream example for one complete field of video is shown in Table XIII. A pseudo code bit stream example for one sequence of fields is shown in Table XIV. An example listing of a field of video in ADV601LC bitstream format appears in Table XVI. Y COMPONENT 6 3 ...
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... Mallat block 30 data—Typical BW = 0x00E4 Mallat block 21 data—Typical BW = 0x0301 Mallat block 27 data—Typical BW = 0x0281 Mallat block 24 data—Typical BW = 0x0281 Mallat block 3 data—Typical BW = 0x23D5 For Mallat Block Number /* Mallat block 6 data */ /* Mallat block 6 data */ /* Required in decode to end field sequence*/ –25– ADV601LC ...
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... ADV601LC Table XV. ADV601LC Field and Block Delimiters (Codes) Code Name Code #SOF1 0xffffffff40000000 #SOF2 0xffffffff41000000 <VITC> (96 bits) <TYPE1> 0x81 <TYPE2> 0x82 <TYPE3> 0x83 <TYPE4> 0x84 #SOB1 0xffffffff81 #SOB2 0xffffffff82 #SOB3 0xffffffff83 #SOB4 0xffffffff84 #SOB5 0xffffffff8f Description (Align all #Delimiter Codes to 32-Bit Boundaries) Start of Field delimiter identifies Field1 data ...
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... NOTE 1 This table shows ADV601LC compressed data for one field in a color ramp video sequence. The SOF# and SOB# codes in the data are in bold text. Bit Error Tolerance Bit error tolerance is ensured because a bit error within a Huffman coded stream does not cause #delimiter symbols to be misread by the ADV601LC in decode mode ...
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... DECODE IS HOST SPECIFIC Using the ADV601LC in Computer Applications Many key features of the ADV601LC were driven by the demand- ing cost and performance requirements of computer applications. The following ADV601LC features provide key advantages in computer applications: • Host Interface The 512 double word FIFO provides necessary buffering of compressed digital video to deal with PCI bus latency. • ...
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... Because the ADV7175 has a CCIR-656 interface, it connects directly with the ADV601LC without “glue” logic. Note that the ADV7175 can only be used at CCIR-601 sampling rates. The ADV7175 example circuit, which appears in Figure 16, is used in this configuration on the ADV601LC Video Lab dem- onstration board. REV. 0 ADR0 A0– ...
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... The following section provides an over- view of only some of the features and how they are achieved with the ADV601LC. Please refer to Figures 2 and 3 as necessary. Higher Compression With Interfield Techniques The ADV601LC normally operates as a field-independent codec ...
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... Permanent damage may occur to devices subjected to high energy electrostatic discharges. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. The ADV601LC latchup immunity has been demonstrated at 100 mA/–100 mA on all pins when tested to industry standard/JEDEC methods. REV. 0 Min 4 ...
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... OL Figure 18. Test Condition Voltage Reference and Device Loading TIMING PARAMETERS This section contains signal timing information for the ADV601LC. Timing descriptions for the following items appear in this section: • Clock signal timing • Video data transfer timing (CCIR-656, and Multiplexed Philips formats) • ...
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... ASSERTED t CTRL_EC_OH Figure 21. CCIR-656 Video—Encode Pixel (YCrCb) Transfer Timing REV VCLK_CYC t VCLKO_D0 t VCLKO_D1 Figure 19. Video Clock Timing VALID t VDATA_DC_D VALID t CTRL_DC_D VALID t VDATA_EC_S ASSERTED t CTRL_EC_D –33– ADV601LC Min Max N N/A N N/A VALID VALID Min Max 2 N/A 5 N/A N N/A VALID t ...
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... ADV601LC Figure 22. CCIR-656 Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLKO. –34– REV. 0 ...
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... CTRL Signals, Decode Slave Multiplexed Philips, Hold CTRL_DSM_H (O) VCLKO (O) VDATA (I) CTRL Figure 24. Multiplexed Philips Video—Decode and Slave Pixel (YCrCb) Transfer Timing REV. 0 VALID t VDATA_DMM_D VALID t CTRL_DMM_D VALID t VDATA_DSM_OH t VDATA_DSM_D VALID t CTRL_DSM_S –35– ADV601LC Min Max N N/A N N/A VALID VALID Min Max N N/A 16 N/A 42 ...
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... ADV601LC Figure 25. Multiplexed Philips Video–Line (Horizontal) and Frame (Vertical) Transfer Timing –36– REV. 0 ...
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... CTRL Signals, Encode Slave Multiplexed Philips Mode, Hold CTRL_ESM_H (I) VCLK (I) VDATA (I) CTRL Figure 27. Multiplexed Philips Video—Encode and Slave Pixel (YCrCb) Transfer Timing REV. 0 VALID t VDATA_EMM_S ASSERTED t CTRL_EMM_D VALID t VDATA_ESM_S ASSERTED t CTRL_ESM_S –37– ADV601LC Min Max 2 N/A 5 N/A N N/A VALID t VDATA_EMM_H Min Max 2 N/A 5 N/A ...
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... Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing The diagrams in this section show transfer timing for host read and write accesses to all of the ADV601LC’s direct registers, except the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers are slower than access timing for the Compressed Data register ...
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... Period) +7.4. WR_D_RDT (MIN) = 4.3 (VCLK Period) +14.8. ACK_D_WRD (MAX) may be as long as 52 VCLK periods. t WR_D_WRC t t WR_D_PWD WR_D_PWA VALID t t ADR_D_WRS ADR_D_WRH VALID t t DATA_D_WRS DATA_D_WRH t ACK_D_WRD t ACK_D_WROH –39– ADV601LC Min Max Unit 1 N/A N N N/A ns – ...
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... Host Interface (Compressed Data) Register Timing The diagrams in this section show transfer timing for host read and write transfers to the ADV601LC’s Compressed Data register. Accesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers ...
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... WR (I) ADR, BE ADR_CD_WRS (I) DATA (O) ACK t Figure 31. Host (Compressed Data) Write Transfer Timing REV WR_CD_WRC t t WR_CD_PWA WR_CD_PWD VALID t ADR_CD_WRH VALID t t DATA_CD_WRS DATA_CD_WRH t ACK_CD_WRD ACK_CD_WROH –41– ADV601LC Min Max Unit N ...
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... ADV601LC Pin Pin Pin Name Type 1 DATA4 I/O 2 DATA3 I/O 3 DATA2 I/O 4 DATA1 I/O 5 DATA0 I/O 6 VDD POWER 7 GND GROUND ADR1 I 12 ADR0 I 13 GND GROUND BE2–BE3 14 I BE0–BE1 GND GROUND RESET VDD POWER ACK VDD ...
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... LCODE FIFO_SRQ 24 25 STATS_R 26 VDD 27 GND 28 GND VDD 29 30 DADR8 *APPLY A 10k REV. 0 PIN CONFIGURATION ADV601LC TOP VIEW (Not to Scale) PULL DOWN RESISTOR TO THIS PIN –43– ADV601LC 90 GND 89 NC* 88 NC* 87 VDATA0 86 VDATA1 85 VDATA2 84 VDATA3 83 VDD 82 GND 81 VDATA4 80 VDATA5 79 VDATA6 ...
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... ADV601LC 0.030 (0.75) 0.025 (0.60) 0.018 (0.45) SEATING 0.003 (0.08) Part Number Ambient Temperature Range ADV601LCJST +70 C NOTES Commercial temperature range ( +70 C Plastic Thin Quad Flatpack. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 120-Lead LQFP (ST-120) 0.638 (16.20) 0.630 (16.00) SQ 0.622 (15.80) 0.063 (1.60) 0.559 (14.20) MAX ...