adv611 Analog Devices, Inc., adv611 Datasheet - Page 40

• Manufacturer Part Number: adv611
• Description: Closed Circuit Tv Digital Video Codec
• Manufacturer: Analog Devices, Inc.

ADV611/ADV612
Host Interface (Indirect Address, Indirect Register Data and Interrupt Mask/Status) Register Timing
The diagrams in this section show transfer timing for host read and write accesses to all of the ADV611/ADV612’s direct registers,
except the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers
are slower than access timing for the Compressed Data register. For information on access timing for the Compressed Data direct
register, see the Host Interface (Compressed Data) Register Timing section. Note that for accesses to the Indirect Address, Indirect
Register Data and Interrupt Mask/Status registers, your system MUST observe ACK and RD or WR assertion timing.
Parameter
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
RD input must be asserted (low) until ACK is asserted (low).
Maximum t
During STATS_R deasserted (low) conditions, t
Minimum t
Maximum t
During STATS_R deasserted (low) conditions, t
RD_D_RDC
RD_D_PWA
RD_D_PWD
ADR_D_RDS
ADR_D_RDH
DATA_D_RDD
DATA_D_RDOH
RD_D_WRT
ACK_D_RDD
ACK_D_RDOH
Figure 32. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Timing
RD_D_WRT
DATA_D_RDD
ACK_D_RDD
Table XXVI. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Read Timing Parameters
(I) ADR, BE, CS
varies with VCLK according to the formula: t
(O) DATA
Description
RD Signal, Direct Register, Read Cycle Time (at 27 MHz VCLK)
RD Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
RD Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
ADR Bus, Direct Register, Read Setup
ADR Bus, Direct Register, Read Hold
DATA Bus, Direct Register, Read Delay
DATA Bus, Direct Register, Read Output Hold (at 27 MHz VCLK)
WR Signal, Direct Register, Read-to-Write Turnaround (at 27 MHz VCLK)
ACK Signal, Direct Register, Read Delayed (at 27 MHz VCLK)
ACK Signal, Direct Register, Read Output Hold (at 27 MHz VCLK)
(O) ACK
varies with VCLK according to formula: t
varies with VCLK according to the formula: t
(I) WR
(I) RD
DATA_D_RDD
ACK_D_RDD
t
DATA D RDD
t
ADR D RDS
VALID
t
ACK D RDD
t
RD D PWA
may be as long as 52 VCLK periods.
may be as long as 52 VCLK periods.
ACK_D_RDD (MAX)
RD_D_WRT (MIN)
DATA_D_RDD (MAX)
t
ACK D RDOH
VALID
t
t
RD D RDC
DATA D RDOH
t
ADR D RDH
–40–
= 7 (VCLK Period) +14.8.
= 1.5 (VCLK Period) –4.1.
t
RD D PWD
= 4 (VCLK Period) +16.
VALID
Min
N/A
N/A
2
2
N/A
48.7
8.6
5
26
11
1
1
4
t
VALID
RD D WRT
Max
N/A
N/A
N/A
N/A
N/A
171.6
N/A
N/A
287.1
N/A
2, 3
5, 6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0