adv202 Analog Devices, Inc., adv202 Datasheet - Page 38

• Manufacturer Part Number: adv202
• Description: Jpeg2000 Video Codec
• Manufacturer: Analog Devices, Inc.

ADV202
HIPI (HOST INTERFACE—PIXEL INTERFACE)
Figure 29 is a typical configuration using HIPI mode.
JDATA INTERFACE
Figure 30 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR656.
HOST CPU
16-BIT
ASIC
DATA[15:0]
ADDR[3:0]
32-BIT HOST
DATA [31:0]
ACK
IRQ
WE
RD
CS
DREQ
DACK
DREQ
DACK
ACK
IRQ
WR
CS
RD
Figure 29. Host Interface—Pixel Interface Mode
JDATA[7:0]
HOLD
VALID
HDATA[15:0]
IRQ
ADDR[3:0]
CS
RD
WE
ACK
Figure 30. JDATA Application
Y0/G0<MSB>
Y0/G0<6>
Y0/G0<5>
Y0/G0<4>
Y0/G0<3>
Y0/G0<2>
Y0/G0<1>
Y0/G0<0>
Cb0/G1<MSB>
Cb0/G1<6>
Cb0/G1<5>
Cb0/G1<4>
Cb0/G1<3>
Cb0/G1<2>
Cb0/G1<1>
Cb0/G1<0>
Y1/G2<MSB>
Y1/G2<6>
Y1/G2<5>
Y1/G2<4>
Y1/G2<3>
Y1/G2<2>
Y1/G2<1>
Y1/G2<0>
Cr0/G3<MSB>
Cr0/G3<6>
Cr0/G3<5>
Cr0/G3<4>
Cr0/G3<3>
Cr0/G3<2>
Cr0/G3<1>
Cr0/G3<0>
ADV202
Rev. C | Page 38 of 40
VDATA[11:2]
74.25MHz
HSYNC
VSYNC
FIELD
MCLK
VCLK
YCrCb
HDATA<31>
HDATA<30>
HDATA<29>
HDATA<28>
HDATA<27>
HDATA<26>
HDATA<25>
HDATA<24>
HDATA<23>
HDATA<22>
HDATA<21>
HDATA<20>
HDATA<19>
HDATA<18>
HDATA<17>
HDATA<16>
HDATA<15>
HDATA<14>
HDATA<13>
HDATA<12>
HDATA<11>
HDATA<10>
HDATA<9>
HDATA<8>
HDATA<7>
HDATA<6>
HDATA<5>
HDATA<4>
HDATA<3>
HDATA<2>
HDATA<1>
HDATA<0>
CS
RD
WE
ACK
IRQ
DREQ0
DACK0
DREQ1
DACK1
MCLK
P[19:10]
FIELD
VS
HS
LLC1
RAW PIXEL
DATAPATH
COMPRESSED
DATAPATH
VIDEO IN