tp3076 National Semiconductor Corporation, tp3076 Datasheet - Page 6

• Manufacturer Part Number: tp3076
• Description: Combo Ii Programmable Pcm Codec/filter For Isdn And Digital Phone Applications
• Manufacturer: National Semiconductor Corporation

www.national.com
EN
Programmable Functions
Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II.
Note 6: The “PS” bit MUST be set to “1” for both transmit and receive for the TP3076.
Note 7: T5 is the MSB of the time-slot assignment bit field. Time-slot bits should be set to “000000” for both transmit and receive when operating in non-delayed
data timing mode.
TIME-SLOT ASSIGNMENT
COMBO II can operate in either fixed time-slot or time-slot
assignment mode for selecting the Transmit and Receive
PCM time-slots. Following power-on, the device is automati-
cally in Non-Delayed Timing mode, in which the time-slot
always begins with the leading (rising) edge of frame sync
inputs FS
used with Delay Data timing; see Figure 3. FS
may have any phase relationship with each other in BCLK
period increments.
Alternatively, the internal time-slot assignment counters and
comparators can be used to access any time-slot in a frame,
using the frame sync inputs as marker pulses for the begin-
ning of transmit and receive time-slot 0. In this mode, a
frame may consist of up to 64 time-slots of 8 bits each. A
time-slot is assigned by a 2-byte instruction as shown in
Table 1 and Table 6. The last 6 bits of the second byte
indicate the selected time-slot from 0–63 using straight bi-
nary notation. When writing a time-slot and port assignment
register, if the PCM interface is currently active, it is imme-
diately deactivated to prevent possible bus clashes. A new
assignment becomes active on the second frame following
the end of the Chip-Select for the second control byte.
Rewriting of the register contents should not be performed
during the talking period of a connection to prevent wave-
form distortion caused by loss of a sample which will occur
with each register write. The “EN” bit allows the PCM input,
D
abled.
Time-Slot Assignment mode requires that the FS
pulses conform to the delayed data timing format shown in
Figure 3.
PORT SELECTION
On the TP3076, the “PS” bit MUST always be set to 1.
7
0
1
R
V
V
V
1, or output, D
IN
IN
IN
= +Full Scale
= 0V
= −Full Scale
(Note 6)
X
PS
and FS
6
1
1
X
1, as appropriate, to be enabled or dis-
R
. Time-Slot Assignment may only be
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
(Note 7)
Bit Number and Name
T
5
X
5
TABLE 6. Time-Slot and Port Assignment Instruction
T
X
4
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
MSB
4
µ255 Law
TABLE 5. Coding Law Conventions
(Continued)
T
3
X
X
3
X
LSB
and FS
and FS
T
X
2
2
R
R
6
T
X
1
1
Table 6 shows the format for the second byte of both trans-
mit and receive time-slot and port assignment instructions.
TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in Table 1
and Table 7. This corresponds to a range of 0 dBm0 levels at
VF
+5.0 dBm to −20.4 dBm in 600Ω).
To calculate the binary code for byte 2 of this instruction for
any desired input 0 dBm0 level in Vrms, take the nearest
integer to the decimal number given by:
and convert to the binary equivalent. Some examples are
given in Table 7. A complete tabulation is given in Appendix
I of AN-614.
It should be noted that the Transmit (idle channel) Noise and
Transmit Signal to Total Distortion are both specified with
transmit gain set to 0 dB (gain register set to all ones). At
high transmit gains there will be some degradation in noise
performance for these parameters. See Application Note
AN-614 for more information on this subject.
Even Bit Inversion
True A-Law with
1 0 1 0 1 0 1 0
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 0 1 0 1 0 1 0
X
MSB
I between 1.375 Vrms and 0.074 Vrms (equivalent to
TABLE 7. Byte 2 of Transmit Gain Instruction
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
1 1 1 1 1 1 1 0
T
X
0
Bit Number
0
—
Disable D
Disable D
Enable D
Enable D
LSB
200 x log
X
R
X
R
1 Output (Transmit Instruction)
1 Input (Transmit Instruction)
1 Output (Transmit Instruction)
1 Input (Receive Instruction)
10
0 dBm0 Test Level (Vrms)
(V/0.07299)
Even Bit Inversion
Function
No Output (Note 8)
1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1
A-Law without
MSB
at VF
0.074
0.075
1.359
—
X
LSB
I