tp3076 National Semiconductor Corporation, tp3076 Datasheet - Page 4

• Manufacturer Part Number: tp3076
• Description: Combo Ii Programmable Pcm Codec/filter For Isdn And Digital Phone Applications
• Manufacturer: National Semiconductor Corporation

www.national.com
Write Transmit Gain Register
Read Transmit Gain Register
Write Receive Time-Slot/Port
Read-Back Receive Time-Slot/Port
Write Transmit Time-Slot/Port
Read-Back Transmit Time-Slot/Port
Functional Description
Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI or CO pin. X = don’t care.
Note 2: “P” is the power-up/down control bit, see Power-up/Down Control section. (“0” = Power Up, “1” = Power Down)
Note 3: Other register address codes are invalid and should not be used.
A decode cycle begins immediately after the assigned re-
ceive timeslot, and 10 µs later the Decoder DAC output is
updated. The total signal delay is 10 µs plus 120 µs (filter
delay) plus 62.5 µs (
190 µs.
PCM INTERFACE
The FS
ning of the 8-bit transmit and receive time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW. Two different relationships
may be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting bit 3 in the
Control Register (see Table 2). Non-delayed data mode is
similar to long-frame timing on the TP3050/60 series of
devices (COMBO); time-slots begin nominally coincident
with the rising edge of the appropriate FS input. The alter-
native is to use Delayed Data mode, which is similar to
shortframe sync timing on COMBO, in which each FS input
must be high at least a half-cycle of BCLK earlier than the
timeslot. The Time-Slot Assignment circuit on the device can
only be used with Delayed Data timing.
When using Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate FS input.
The actual transmit and receive time-slots are then deter-
mined by the internal Time-Slot Assignment counters.
Transmit and Receive frames and time-slots may be skewed
from each other by any number of BCLK cycles. During each
assigned Transmit time-slot, the D
from the PCM register on the rising edges of BCLK. TS
also pulls low for the first 7
control the TRI-STATE Enable of a backplane line-driver.
Serial PCM data is shifted into the D
assigned Receive time-slot on the falling edges of BCLK.
SERIAL CONTROL PORT
Control information and data are written into or read-back
from COMBO II via the serial control port consisting of the
control clock CCLK, the serial data input, CI, and output, CO,
and the Chip Select input, CS. All control instructions require
2 bytes, as listed Table 1, with the exception of a single byte
power-up/down command. The Byte 1 bits are used as
follows: bit 7 specifies power up or power down; bits 6, 5, 4
and 3 specify the register address, bit 2 specifies whether
the instruction is read or write; bit 1 specifies a one or two
byte instruction; and bit 0 is not used.
To shift control data into COMBO II, CCLK must be pulsed
high 8 times while CS is low. Data on the CI input is shifted
X
and FS
Function
R
frame sync inputs determine the begin-
1
⁄
2
frame) which gives approximately
1
⁄
2
bit times of the time-slot to
TABLE 1. Programmable Register Instructions (Continued)
X
1 output shifts data out
R
1 input during each
(Continued)
7
P
P
P
P
P
P
6
0
0
1
1
1
1
Byte 1 (Notes 1, 2, 3)
5
1
1
0
0
0
0
X
4
0
0
0
0
1
1
1
4
3
1
1
1
1
0
0
into the serial input register on the falling edge of each CCLK
pulse. After all data is shifted in, the contents of the input
shift register are decoded, and may indicate that a 2nd byte
of control data will follow. This second byte may either be
defined by a second byte-wide CS pulse or may follow the
first contiguously, i.e, it is not mandatory for CS to return high
between the first and second control bytes. At the end of
CCLK8 in the 2nd control byte the data is loaded into the
appropriate programmable register. CS may remain low con-
tinuously when programming successive registers, if de-
sired. However, CS must be set high when no data transfers
are in progress.
To readback Interface Latch data or status information from
COMBO II, the first byte of the appropriate instruction is
strobed while CS is low, as defined in Table 1. CS must be
kept low, or be taken low again for a further 8 CCLK cycles,
during which the data is shifted onto the CO pin on the rising
edges of CCLK. When CS is high the CO pin is in the
high-impedance TRI-STATE, enabling the CI and CO pins of
many devices to be multiplexed together.
If CS returns high during either byte 1 or byte 2 before all
eight CCLK pulses of that byte occur, both the bit count and
byte count are reset and register contents are not affected.
This prevents loss of synchronization in the control interface
as well as corruption of register data due to processor inter-
rupt or other problem. When CS returns low again, the
device will be ready to accept bit 1 of byte 1 of a new
instruction.
Programmable Functions
POWER-UP/DOWN CONTROL
Following power-on initialization, power-up and power-down
control may be accomplished by writing any of the control
instructions listed in Table 1 into COMBO II with the “P” bit
set to “0” for power-up or “1” for power-down. Normally it is
recommended that all programmable functions be initially
programmed while the device is powered down. Power state
control can then be included with the last programming
instruction or the separate single-byte instruction. Any of the
programmable registers may also be modified while the
device is powered-up or down by setting the “P” bit as
indicated. When the power-up or down control is entered as
a single byte instruction, bit one (1) must be reset to a 0.
When a power-up command is given, all de-activated circuits
are activated, but the TRI-STATE PCM output(s), D
remain in the high impedance state until the second FS
pulse after power-up.
2
0
1
0
1
0
1
1
1
1
1
1
1
1
0
X
X
X
X
X
X
7
6
5
Byte 2 (Note 1)
See Table 7
See Table 7
See Table 6
See Table 6
See Table 6
See Table 6
4
3
2
X
1
1 will
X
0